Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
rluker5 Wasn't Zen 4 4 wide, Zen 5 6 wide, and now Zen 6 will be 8 wide so on that, with 512 staying basically the same, the uplift could be less than from 4 to 5, or it could be more due to other things not clearly explained here. I'm skeptical of the ground up redesign though as I've heard that from AMD a few times before when it wasn't really true. It is definitely an improvement and the rumored 50% increase in cores per CCD will really help single CCD CPUs in some tasks, but the experience for most will likely be more dependent on clockspeed and IPC gains from the node change as the vast majority of common user tasks aren't significantly benefitted by using over 8 cores. If the node improvement isn't enough to offset the added heat from the added cores and wideness then sustained cockspeeds will be lower, as opposed to the rumors of 6, 6.5, 7.0 clocks. Heat comes from compute per second per area at a given efficiency. AMD is doing what they should with node improvements IMO as they are balancing the responsiveness of high clockspeeds with the inefficiency of high clockspeeds by using the improved efficiency of the node improvement to get more done per clock instead of going too far up the inefficiency curve. It isn't everything at once but getting the best practical outcome by balancing several related variables. It seems like AMD and Intel both do this and are both limited by node improvements (per core) and silicon expenditures (multicore, cache quantity) when it comes to CPU generational improvements. And a good example of where architectural design improvements outpaced node improvements is Rocket Lake. And a good example of going too far up the inefficiency curve on clockspeeds is Raptor Lake, especially when voltages were handled in some outdated archaic fashion with the built for Haswell LLC settings that were exacerbated by motherboard manufacturers giving a dirty all core undervolt at the expense of single core overvolt. I don't think many want to see Zen 6 repeat either of these mistakes and most would prefer an architecture and execution to best balance the opportunities and limitations given by the node and how much AMD is willing to spend on silicon per CPU. Don't hype yourself up too much from rumors and you won't be as disappointed with reality. The I/O die could bring some extra noticeable improvements though. Reply
jp7189 I'd like to hear more about the IOD. There should be some new tricks there to help feed the beast. Dare I hope for quad channel on the desktop? Bad timing with current memory prices. At the least, I expect the platform to be optimized for high RAM clockspeeds. Reply
George³ rluker5 said: Wasn't Zen 4 4 wide, Zen 5 6 wide, and now Zen 6 will be 8 wide so on that No, ZEN 5&6 have same front end 8 wide. Reply
thisisaname I wonder if I'll be able to buy any memory or storage to go with this new CPU. Reply
gondor rluker5 said: Wasn't Zen 4 4 wide, Zen 5 6 wide, and now Zen 6 will be 8 wide so on that, with 512 staying basically the same, the uplift could be less than from 4 to 5, or it could be more due to other things not clearly explained here. I'm skeptical of the ground up redesign though as I've heard that from AMD a few times before when it wasn't really true. It is definitely an improvement and the rumored 50% increase in cores per CCD will really help single CCD CPUs in some tasks, but the experience for most will likely be more dependent on clockspeed and IPC gains from the node change as the vast majority of common user tasks aren't significantly benefitted by using over 8 cores. If the node improvement isn't enough to offset the added heat from the added cores and wideness then sustained cockspeeds will be lower, as opposed to the rumors of 6, 6.5, 7.0 clocks. Heat comes from compute per second per area at a given efficiency. AMD is doing what they should with node improvements IMO as they are balancing the responsiveness of high clockspeeds with the inefficiency of high clockspeeds by using the improved efficiency of the node improvement to get more done per clock instead of going too far up the inefficiency curve. It isn't everything at once but getting the best practical outcome by balancing several related variables. It seems like AMD and Intel both do this and are both limited by node improvements (per core) and silicon expenditures (multicore, cache quantity) when it comes to CPU generational improvements. And a good example of where architectural design improvements outpaced node improvements is Rocket Lake. And a good example of going too far up the inefficiency curve on clockspeeds is Raptor Lake, especially when voltages were handled in some outdated archaic fashion with the built for Haswell LLC settings that were exacerbated by motherboard manufacturers giving a dirty all core undervolt at the expense of single core overvolt. I don't think many want to see Zen 6 repeat either of these mistakes and most would prefer an architecture and execution to best balance the opportunities and limitations given by the node and how much AMD is willing to spend on silicon per CPU. Don't hype yourself up too much from rumors and you won't be as disappointed with reality. The I/O die could bring some extra noticeable improvements though. So. Much. Nonsense. Did you LLM it up? Reply
evolucion888 gondor said: So. Much. Nonsense. Did you LLM it up? Word! So much nonsense. Reply
usertests rluker5 said: It is definitely an improvement and the rumored 50% increase in cores per CCD will really help single CCD CPUs in some tasks, but the experience for most will likely be more dependent on clockspeed and IPC gains from the node change as the vast majority of common user tasks aren't significantly benefitted by using over 8 cores. 12-core CCD is pretty certain along with increases in L3 cache. IPC and clocks are where it will get interesting, with the big claims. There could be some unexpected outcomes, such as the cheapest Zen 6 non-X3D part matching the 9800X3D in gaming from a combo of 48 MiB L3, higher IPC, and higher clocks. Zen 5 mobile had double-pumped AVX-512 while desktop had full-width, so that's something to look into when mobile Zen 6 arrives. Reply
rluker5 gondor said: So. Much. Nonsense. Did you LLM it up? That first bit I got from wikipedia so sorry about thinking Zen 6 will have a wider front end than Zen 5. Should have went to Chips and Cheese, but I ran out oftime. Reply
Notton thisisaname said: I wonder if I'll be able to buy any memory or storage to go with this new CPU. If you're using AM5, you can reuse your old stuff. Desktop Zen 6 is supposedly coming out on AM5, so all you need is a BIOS update to run it on existing hardware. Zen 7 is also rumored to be AM5. 2028 is when AMD will offer Zen 8, and socket AM6 for DDR6. At least, according to rumors and roadmaps. Seeing as how crazy pricing is with the AI bubble, my money is on AM4 becoming AM4ever. Reply
bit_user rluker5 said: Wasn't Zen 4 4 wide, Zen 5 6 wide, and now Zen 6 will be 8 wide so on that, with 512 staying basically the same, No, where did you get any of that? Why post this stuff if you're not going to take the time to get it right? Zen 4 had a 4-wide decoder, but 6-wide dispatch (source: https://chipsandcheese.com/p/amds-zen-4-part-1-frontend-and-execution-engine ). Zen 5 moved up to a pair of 4-wide decoders and 8-wide dispatch (source: https://chipsandcheese.com/p/amds-strix-point-zen-5-hits-mobile ) As for AVX-512, Zen 4 famously had the half-width implementation (which AMD somewhat misleadingly referred to as "double-pumped"). Zen 4 had 2x 256-bit FMA ports, 2x 256-bit FADD ports, and 2x FStore ports (source: https://chipsandcheese.com/p/amds-zen-4-part-1-frontend-and-execution-engine ) With Zen 5, the desktop & server cores went tho full 512-bit width and the latency of FADD was cut from 3 to 2 cycles (source: https://chipsandcheese.com/p/amds-ryzen-9950x-zen-5-on-desktop ). As for Zen 6, the source doesn't say anything about the vector/FP width. rluker5 said: the vast majority of common user tasks aren't significantly benefitted by using over 8 cores. L3 size will naturally increase, as a consequence of more cores per CCD. The CCD-IOD link will also greatly improve, which is something we've already seen in Strix Halo (Ryzen AI Max). rluker5 said: If the node improvement isn't enough to offset the added heat from the added cores and wideness then sustained cockspeeds will be lower, If they're talking about 8-wide dispatch, then it's the same as Zen 5. Also, gaming is notoriously low-IPC, which could support higher boost speeds than AVX-heavy number crunching workloads. Reply
Key considerations
- Investor positioning can change fast
- Volatility remains possible near catalysts
- Macro rates and liquidity can dominate flows
Reference reading
- https://www.tomshardware.com/pc-components/cpus/SPONSORED_LINK_URL
- https://www.tomshardware.com/pc-components/cpus/amd-pubs-first-zen-6-document-for-developers-a-brand-new-8-wide-cpu-core-with-strong-vector-capabilities#main
- https://www.tomshardware.com
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