When you purchase through links on our site, we may earn an affiliate commission. Here’s how it works .
(Image credit: Getty Images / NurPhoto) Share Share by: Copy link Facebook X Whatsapp Reddit Flipboard Share this article Join the conversation Follow us Add us as a preferred source on Google Tom's Hardware Premium Roadmaps
Chinese researchers have developed a capacitor-less DRAM-like memory cell that uses two transistors (2T0C) with dual-gate control, built at a 4F² minimum area, reports TrendForce, citing ResearchGate . The new memory cell architecture uses a self-aligned process. It promises to achieve reliable multi-bit storage, fast DRAM-like write times, and extended retention without a discrete storage capacitor, according to its developers. While it's not a DRAM replacement for now, it could become a viable solution for various eDRAM and stacked 3D memory applications.
Sanctions imposed by the U.S. and its allies on China's semiconductor sector greatly limit the capabilities of the People's Republic to produce chips on advanced production nodes, as companies like CXMT, SMIC, and YMTC do not have access to the latest tools. However, curbing pathfinding, research, and development (R&D) in academia is considerably harder (if possible at all), which is why Chinese scientists can conduct world-class research and develop innovative technologies that are on par with the West.
Before we proceed, let's establish some terminology to avoid confusion. In semiconductor memory discussions, 4F², dual-gate 4F², and 4F² 2T0C are often used interchangeably, even though they describe different layers of the design stack. While all three can appear in the same sentence, each answers a fundamentally different question: how dense the cell is, how the transistor is built, and how the bit is stored.
HBM undergoes major architectural shakeup as TSMC and GUC detail HBM4, HBM4E and C-HBM4E
Chinese memory maker CXMT prepares $4.2 billion USD IPO to take advantage of tight memory market
China's banned memory-maker CXMT unveils surprising new chipmaking capabilities despite crushing US export restrictions
4F² is a layout and density metric that defines the minimum possible area of a memory cell — four times the square of the process feature size — and says nothing about the internal structure of the cell. A 4F² footprint can host a classic 1T1C DRAM cell, an SRAM bitcell, or even a resistive memory element.
The term ' dual-gate ' describes a device-level detail: a dual-gate transistor uses two independently controlled gates to improve electrical control over the channel, reduce leakage, and stabilize threshold voltage. Dual-gate transistors are widely used in the semiconductor industry in logic (FinFET is a dual-gate transistor), SRAM, or DRAM-like cells.
Finally, 4F² 2T0C describes the actual memory architecture featuring two transistors that store data without a dedicated capacitor by relying instead on charge retained in a transistor channel or floating node. This design gives the cell DRAM-like behavior: it still needs refresh, but avoids the scaling challenges associated with deep capacitors.
When combined, the phrase 'dual-gate 4F² 2T0C memory' means a capacitor-less DRAM cell, based on dual-gate transistors, with DRAM-class density at a minimum. In short, we are dealing with three separate concepts combined in a unique design, rather than a singular invention.
Being unconstrained by curbs set by the U.S. and allies, National Key Laboratory of Integrated Circuit Manufacturing Technology at the Institute of Microelectronics of Chinese Academy of Sciences (IME CAS) teamed up with the Beijing Superstring Academy of Memory Technology (SAMT), and Shandong University to develop a 4F² 2T0C memory cell architecture that can store two bits of data per-cell (4 levels of charge), offering a write latency of around 50ns, and data retention for up to 470 seconds, making it a viable memory technology. However, while this isn't a DRAM killer, it may be a potent candidate for embedded DRAM and stacked 3D memory built on top of logic.
The 4F² dual-gate 2T0C memory cell architecture developed by researchers at IME CAS uses two vertical IGZO transistors—one for write (TW) and one for read (TR)—that share a common storage node (SN). Dual-gate operation improves electrostatic control and read stability, enabling capacitor-less, multi-bit storage (2 bits demonstrated) within a compact 4F² footprint. The scientists used a self-aligned single-step (SASS) process to build the cell.
Tests conducted by IME CAS scientists prove that the vertical dual-gate transistor combines high drive current with a sharp turn-on, which makes it easier to clearly distinguish stored charge levels during reads. The cell can hold data for about 470–500 seconds for '1' and '0,' respectively, which is inherently higher than that of DDR5 (which counts in milliseconds), but it is certainly not enough for a storage device.
In addition, the cell can complete a write operation in roughly 50ns, according to its developers. While a 50ns latency is comparable to that of DDR5 (which is about 20 – 40ns), read latency is much more important for real-world performance, but since it depends on sense amplifier architecture (keep in mind that we are dealing with multi-bit storage here) and the actual system, scientists from IME CAS do not publish it.
Reliability testing at 85°C confirms that the device remains stable under prolonged thermal and electrical stress, and threshold voltage shifts are limited to −22.6 mV under negative bias temperature stress (NBTS) and 87.7 mV under positive bias temperature stress (PBTS). A threshold-voltage shift below about 100 mV is considered functionally benign because it does not materially change the transistor’s on/off behavior, timing, or noise margins, so seeing <100 mV shifts at 85°C under accelerated stress can be considered as strong stability (especially for IGZO transistors that are vulnerable to bias stress).
The magic behind the reliable operation of the 2-bit 4F² dual-gate 2T0C memory cell, as well as its solid retention time, is the usage of both gates of the read and write transistors as capacitive contributors to the same storage node, which doubles storage node capacitance (C SN ) compared to single-gate cells, without increasing overall area. As a result, the 2-bit 4F² dual-gate 2T0C memory cell architecture can enable both high density and high reliability at a small area.
China claims domestically-designed 14nm logic chips can rival Nvidia's 4nm
Key considerations
- Investor positioning can change fast
- Volatility remains possible near catalysts
- Macro rates and liquidity can dominate flows
Reference reading
- https://www.tomshardware.com/pc-components/dram/SPONSORED_LINK_URL
- https://www.tomshardware.com/pc-components/dram/chinese-researchers-hail-breakthrough-in-dram-like-cells-which-could-be-used-in-embedded-or-3d-stacked-memory-absence-of-manufacturing-detail-casts-doubt-on-mass-production#main
- https://www.tomshardware.com
- NVIDIA DGX SuperPOD Sets the Stage for Rubin-Based Systems
- NVIDIA Unveils New Open Models, Data and Tools to Advance AI Across Every Industry
- AMD is unfazed by Panther Lake's big integrated GPU — 'It's not even a fair fight' to compare the Arc B390 to Strix Halo, AMD exec claims
- Woot's 'reconditioned' MSI PC deals might be your ticket to an affordable upgrade — For $719, get an RTX 5060-based 14400F PC with 16GB of DDR5 and 1TB of stora
- NVIDIA DLSS 4.5, Path Tracing and G-SYNC Pulsar Supercharge Gameplay With Enhanced Performance and Visuals
Informational only. No financial advice. Do your own research.