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Scientists at IME CAS used its proprietary self-aligned single-step (SASS) production flow to build their 4F² dual-gate 2T0C memory cell. The SASS flow enables the entire vertical dual-gate 2T0C sidewall stack to be built in just one lithography and etch step that simultaneously patterns all pre-deposited layers. This means that write (TW) and read (TR) transistors are formed simultaneously rather than stacked in separate passes, which excludes misalignment and repeated thermal/contamination exposure, which potentially improves yields.
In the demonstrated 4F² vertical cell, the channel height is 120nm, the IGZO channel thickness is ~6nm (it is deposited using atomic layer deposition), and the effective gate length is ~40 nm, as seen in the cross-sectional TEM image. The TEM image also confirms a ~90° vertical sidewall with no top/bottom-device misalignment.
As noted above, the SASS process produces the full stack in one lithography/etch step that patterns pre-deposited layers, which is a fairly simplistic manufacturing method.
First, the researchers deposit a full multilayer stack on the wafer. This stack already includes everything the cell will need later: 30nm of indium tin oxide for ground (GND), the bit line (BL), and the storage node (SN); 40nm of tantalum for the read and write word lines (RWL/WWL); and 40 nm layers of silicon oxide to electrically isolate them. Altogether, the structure consists of five electrode layers separated by four SiOx layers, all deposited before any patterning takes place.
Next comes the main SASS step. Using one lithography mask and one vertical etch, the process cuts through the entire pre-deposited stack at once. This single etch step patterns all five electrode layers and four insulating layers at the same time into a clean vertical sidewall. Since everything is defined in one cut, the write and read transistors are perfectly aligned by design: there are no overlay errors from multiple patterning steps, which is why it is called 'self-aligned.'
Once the sidewall is in place, it is turned into an active device. The exposed tantalum is heated in oxygen at 400 °C, where it self-oxidizes to form a ~9 nm tantalum-oxide high-k gate dielectric directly on the metal. The vertical surface is then coated layer by layer: a ~6 nm IGZO channel is deposited using ALD, followed by the second gate stack, made up of a ~15 nm hafnium-oxide dielectric and a ~25 nm indium-zinc-oxide conductive gate layer.
Despite detailed knowledge of device-level and vertical nanometer-scale dimensions, the absence of disclosed lateral half-pitch information prevents mapping the IME CAS process to a specific DRAM node. Keeping in mind that we are dealing with a research-grade materials stack and have no idea about yields, any general assessment of the cost efficiency of the process would be inaccurate.
That said, while the production flow looks simple and the lack of capacitors opens doors for eDRAM applications (as logic nodes are not exactly great for producing DRAM-class capacitors), there are questions about the practicality of 4F² dual-gate 2T0C memory. First up, a multi-level cell architecture requires advanced sense amplifiers that are both complex and power hungry, something not appreciated by embedded applications. Secondly, while IGZO TFTs are mature in displays as feature sizes are fairly large and yields are high (and forgiving), memory arrays demand dramatically smaller sizes, and defects are not forgiving.
Given all the uncertainties, it is impossible to assess whether IME CAS's 4F² dual-gate 2T0C memory architecture makes sense for commercial applications.
Chinese researchers from IME CAS have demonstrated a 4F² dual-gate 2T0C, capacitor-less DRAM-like memory cell that reaches the minimum DRAM-class cell area without using a storage capacitor.
The cell is fabricated using a self-aligned single-step (SASS) process and is based on two vertical IGZO transistors sharing a common storage node. Tests conducted by IME CAS show 2-bit storage per cell, write times of around 50ns, and data retention of roughly 470–500 seconds, while the devices remain stable at 85°C. Meanwhile, the dual-gate design enhances retention by increasing the effective storage-node capacitance without increasing the cell area.
For now, 4F² dual-gate 2T0C DRAM-like memory is not a replacement for commodity DRAM. Yet, the work points to a route for embedded and 3D-stacked memory. However, the absence of disclosed lateral pitch, information about manufacturability, the multi-level cell architecture, and uncertainties about the feasibility of IGZO TFTs for mass production of memory cast doubt about the future of this memory architecture. But although we can question the practical applicability of 4F² dual-gate 2T0C DRAM-like memory architecture for existing applications and products, this does not belittle the achievement of Chinese scientists, who managed to make this technology work.
Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
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Reference reading
- https://www.tomshardware.com/pc-components/dram/SPONSORED_LINK_URL
- https://www.tomshardware.com/pc-components/dram/chinese-researchers-hail-breakthrough-in-dram-like-cells-which-could-be-used-in-embedded-or-3d-stacked-memory-absence-of-manufacturing-detail-casts-doubt-on-mass-production#main
- https://www.tomshardware.com
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