Ex-Intel CEO Pat Gelsinger praises cutting-edge Nvidia chip production with TSMC on US soil, despite Intel missing out
Developing a new process technology from scratch is a particularly complex, multidisciplinary endeavor that takes 5 or more years these days, from inception to yield ramp. A development cycle of a fabrication technology begins with pathfinding, materials research, transistor structure development, and then running countless TCAD simulations to model doping, strain, and leakage for a new transistor.
Rapidus has licensed its 2nm GAA transistor structure from IBM, but it is also possible to license a chunk of similar technologies from imec and CEA-Leti, public-private R&D institutes. But while it is hard to overestimate the importance of the right transistor structure, this is only the start.
Once transistor technology is complete, engineers build thousands of tightly coupled process steps organized into FEOL, MOL, and BEOL modules — covering transistor formation, interconnects, and metallization. Each of these steps demands atomic-level precision in deposition, etch, lithography, and anneal. Tuning those steps (each with hundreds, if not thousands, of parameters) for manufacturability, uniformity, reliability, defectivity, power, and performance requires decades of engineering experience and time from the team. At this point, technology providers like IBM, Imec, or CEA-Leti cannot really help.
Once each deposition, etch, implant, lithography, and anneal step is stable in isolation, engineers start combining modules (e.g., transistor gate stack and source/drain) on test wafers and tune their sequencing and temperature budgets to prevent cross-contamination or material degradation. This is essentially when the ordered stack of hundreds of steps that define the node — the process flow — takes shape. Again, these integration recipes are not available for licensing from R&D companies or institutes.
After device performance, power, and yield meet targets, the process must be made design-usable by generating PDKs, SPICE models, verified standard-cell libraries for EDA tools, and IPs for chip designers. At the same time, engineers begin implementing the fabrication process in actual fabs and production lines. That implementation and setting the right parameters for equipment is another challenge that demands experience, not something money can buy.
Finally, fabs must achieve high yields in mass production, which is a hard, long, and iterative process involving plenty of experienced engineers. Can this all be done from scratch in a mere five years by a newcomer? Rapidus will show in 2027.
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Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
logainofhades In other words Jensen doesn't want any potential competition. Reply
Gururu I don't doubt Musk can do it with the sheer wealth he commands. Reply
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Reference reading
- https://www.tomshardware.com/tech-industry/semiconductors/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/semiconductors/elon-musk-says-terafab-chip-fab-may-be-the-only-answer-to-teslas-colossal-ai-semiconductor-demand-nvidia-ceo-jensen-huang-warns-against-extremely-hard-challenge#main
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