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Luke James Social Links Navigation Contributor Luke James is a freelance writer and journalist. Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory.
thestryker While this seems to be slightly more practical than prior designs I'm not sure it's viable. The density for compute isn't viable at all and since they're temperature constrained it doesn't seem like something that can rapidly be shrunk. It is possible that some sort of purpose built systems could leverage this, but I have a hard time imagining it would be at scale. Stacking is very likely to be the way to go for the foreseeable future since mixing manufacturing processes can be done there. Transistor design seems to be a far more pressing issue on the compute side and memory makers seem to be looking at leveraging some level of compute within their DRAM. An interesting video that talks about the future of compute: IS5FovPfvf0 View: https://youtu.be/IS5FovPfvf0?si=tVIlK7ODG-7qEgFR Reply
edzieba The first bulk Silicon IC with stacked memory-over-logic, maybe. But a partially non-silicon process has already been announced, gone into mass production, then shuttered again: the Chalcogenide process used to make 3D Xpoint/Optane. This had CMOS compute at the bottom, followed by alternating metal layers and Chalcogenide PCM layers stacked on top, within the same die. Reply
usertests The group further argues that the architecture could eventually deliver 100-fold to 1,000-fold improvements in energy-delay product, a combined metric of speed and efficiency, by continuing to scale vertical integration rather than shrinking transistors. How about using metrics that make sense, or multiple metrics for a better comparison? I've followed Skywater for a long time. If they can legitimately create something with 10-100x better performance per watt than a TSMC N2 chip, then computing could become exciting again, even if there are a few asterisks. Reply
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Reference reading
- https://www.tomshardware.com/tech-industry/semiconductors/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/semiconductors/stanford-led-team-builds-3d-ai-chip-at-us-foundry-reports-4x-performance-gains#main
- https://www.tomshardware.com
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