ZAM is designed to offer two to three times the capacity of HBM, operating at as little as half the power, while being up to 60% cheaper to produce, as reported by Nikkei . Saimemory will try to hit these lofty goals by vertically stacking more DRAM and using Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) to reduce latency between the individual chips.
ZAM is built on the foundational work Intel completed as part of the Advanced Memory Technology R&D program, managed by the U.S. Department of Energy and National Nuclear Security Administration through the Sandia National Laboratory . They recognized that HBM has impressive bandwidth, but trades that for lower capacity and weaker power efficiency. Using Intel’s new bonding techniques and novel DRAM stacking techniques allows for all the benefits of HBM, without those traditional downsides.
“Intel’s Next Generation DRAM Bonding (NGDB) initiative has demonstrated a novel memory architecture and revolutionary assembly methodology that significantly increases DRAM performance, reduces power consumption, and optimizes memory costs,” said Dr. Joshua Fryman, Intel Fellow and CTO of Intel Government Technologies. “Standard memory architectures aren’t meeting AI needs, so NGDB defined a whole new approach to accelerate us through the next decade.”
In developing the NGDB for ZAM, Intel and Sandia had to design a new stacking approach and a different way of organizing the DRAM chips. Early prototypes confirmed it was possible to increase capacity through new stacking techniques, while recent developments have demonstrated that the necessary high performance is there. That’s why Intel and partners are now able to move forward with developing the first real prototypes of Z-Angle memory.
Gwen Voskuilen, principal member of technical staff at Sandia, said, “This is an exciting technology that we anticipate will lead to a wider adoption of higher bandwidth memories in systems that are currently unable to take advantage of high bandwidth memory due to its limited capacity and power constraints.”
This venture isn’t designed to suddenly bring new DDR5 or HBM production online, though. It’s looking beyond what’s currently available to data center builders and hoping to provide what they might need next.
Saimemory is slated to produce its first ZAM prototype sometime in 2027, with plans to develop a mass production line for the new memory by 2029.
Micron plans $9.6 billion HBM fab in Japan as AI memory race accelerates
Key considerations
- Investor positioning can change fast
- Volatility remains possible near catalysts
- Macro rates and liquidity can dominate flows
Reference reading
- https://www.tomshardware.com/tech-industry/artificial-intelligence/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/artificial-intelligence/intel-is-co-developing-new-z-angle-memory-to-compete-with-hbm-used-in-ai-data-centers-vertically-stacked-memory-touts-2-to-3x-more-capacity-greater-bandwidth-and-half-the-power-consumption#main
- https://www.tomshardware.com
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Informational only. No financial advice. Do your own research.