ASML launches revolutionary lithography scanner for advanced 3D chip packaging — Twinscan XT:260 machine quadruples throughput
Silicon is used because it supports very high wiring density, tight dimensional control, and thermal expansion behavior that is designed to match logic and memory dies. However, properties of organic substrates sometimes do not match those of silicon interposers (limited wiring density, warpage at large sizes, weaker thermal and mechanical stability, etc.), which is why established players like AMD, Intel, and Samsung are exploring glass-core substrates for their next-generation packaging flows.
Glass-based substrates offer clear advantages over traditional organic materials, including excellent flatness that enables exceptional dimensional control, which is a key requirement for dense interconnects in advanced system-in-packages (SiPs) built from multiple chiplets. In addition, glass delivers stronger thermal performance and mechanical rigidity, enabling it to tolerate higher operating temperatures and harsher conditions typical of data center–class SiPs. As a result, glass substrates are particularly well matched for AI and cloud processor designs that tend to rely on large, complex, and thermally demanding multi-die packages. Yet, glass substrates are currently in development and are not in mass production.
Panel-level packaging refers to processing chip packages on large rectangular panels rather than round wafers, and today it is used mainly in fan-out panel-level packaging (FOPLP) for some automotive, power, RF, and wearable solutions, though they are not yet common. PLP offers clear advantages over 300-mm wafers: they can offer more efficient manufacturing and a larger package. However, currently, there are no higher-end semiconductor packaging tools that can enable front-end-like processing on panels. As a result, PLP for AI and HPC packages is still in the development stage at Intel and Samsung. That said, the ongoing work on glass-based panels suggests PLP could become viable in the late 2020s at the earliest, initially as a way to replace very large organic substrates and potentially complement (but not fully replace) silicon interposers in advanced AI system-on-chips (SoCs).
Meanwhile, Rapidus seems to plan to wed PLP with glass substrates from the very start, though it is unclear when it intends to do so. Nonetheless, Rapidus's ambitions to be ahead of the industry clearly highlight the company's aggressive plans to become a leading chipmaker right from the very start.
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Reference reading
- https://www.tomshardware.com/tech-industry/semiconductors/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/semiconductors/rapidus-explores-panel-level-packaging-on-glass-substrates-for-next-generation-processors-aggressive-plan-would-help-it-leapfrog-rivals#main
- https://www.tomshardware.com
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