
Intel’s EMIB (Embedded Multi-die Interconnect Bridge) technology connects chiplets using tiny silicon bridges embedded directly in the package substrate, eliminating the need for a large silicon interposer. This reduces both cost and thermal complexity, especially for designs that don’t need the wide I/O bandwidth or power delivery footprint of full CoWoS. Intel’s Foveros technology, by contrast, vertically stacks dies using through-silicon vias or direct copper bonding. It offers high interconnect density and heterogeneous node integration, at the cost of more stringent thermal and yield considerations.
TSMC’s CoWoS-L remains the go-to option for high-performance AI GPUs and HBM-heavy accelerators. Its capacity, however, is finite. TSMC is planning larger interposer sizes of up to 9.5x reticle by 2027, but that expansion is not arriving fast enough for the industry’s current volume requirements. Nvidia is increasing orders for H200 and B100 accelerators, both of which require extensive CoWoS packaging and high-stack HBM.
Intel has confirmed that some customer designs initially scoped for CoWoS have been ported to Foveros without modification. Its New Mexico facility, which handles both EMIB and Foveros packaging, is being scaled up by 30% and 150% respectively. Unlike TSMC , Intel’s packaging lines are not yet at saturation, and its U.S. location aligns with recent government funding and client interest in onshore manufacturing.
EMIB provides enough die-to-die bandwidth for inference accelerators, network ASICs, and other lower-bandwidth workloads, while sidestepping CoWoS’s cost and capacity constraints. It also supports integration with HBM via EMIB-T, which adds through-silicon vias (TSVs) for memory stacking without full interposers.
While Intel hasn’t formally named customers, MediaTek and Marvell were identified in recent reporting from DigiTimes as evaluating Intel’s packaging for second-tier AI ASICs. Both companies have existing ASIC roadmaps with inference-class acceleration and have previously worked with non-TSMC foundries.
Qualcomm and Apple have gone further, adding EMIB and Foveros to internal job postings. Apple recently advertised a DRAM Packaging Engineer role listing experience with CoWoS, EMIB, and SoIC as desirable. Qualcomm listed EMIB in a position description focused on advanced server packaging, suggesting that its data center ambitions may involve Intel’s technology. While these listings don’t confirm anything solid, they indicate technical alignment and internal exploration. Broadcom has also been mentioned in several analyst briefings as a prospective client.
TrendForce cautions that while there’s real interest in EMIB, current evaluation doesn’t necessarily mean that Apple or Qualcomm will ship Intel-packaged products in the near term. Nonetheless, the presence of these companies in packaging-focused hiring pipelines shows a deliberate move to hedge their bets. At a minimum, they are preparing for a supply chain where CoWoS access is no longer guaranteed.
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Key considerations
- Investor positioning can change fast
- Volatility remains possible near catalysts
- Macro rates and liquidity can dominate flows
Reference reading
- https://www.tomshardware.com/tech-industry/semiconductors/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/semiconductors/intel-gains-ground-in-ai-packaging-as-cowos-capacity-remains-stretched#main
- https://www.tomshardware.com
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