This is the first time an autonomous agent has built a working CPU from spec to GDSII layout file, according to Verkor. The resulting processor — VerCore — is a five-stage pipelined, in-order, single-issue core that met timing at 1.48 GHz on the ASAP7 7nm process design kit, scoring 3,261 on the CoreMark benchmark. Verkor’s paper goes into detail on the pipeline architecture, which includes instruction fetch, decode, execute, memory, and writeback stages with early branch resolution and operand forwarding.
During optimization, the system independently implemented a fast Booth-Wallace multiplier that clocked at 2.57 GHz and a one-cycle branch penalty design that the agent selected after implementing and testing both one-cycle and two-cycle variants. Verkor compares VerCore's CoreMark performance to Intel's Celeron SU2300, a 2011 mobile chip based on the Penryn architecture . A five-stage in-order core with no caches and no out-of-order execution is a fairly straightforward design by industry standards. Verkor's own paper notes that leading-edge chips cost north of $400 million and take 18 to 36 months with engineering teams in the hundreds, but VerCore is far simpler than those designs. That said, the 12-hour timeline is still notable for a fully autonomous run from spec to layout, even if it did require "many tens of billions of tokens" at this comparatively pale level of complexity.
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VerCore hasn’t been physically fabricated and was instead verified in simulation using Spike, a reference RISC-V ISA simulator, and ASAP7 is an academic process design kit, not a production 7nm node. Verkor says it can run a uCLinux variant in simulation. Verkor's paper is candid about the limitations of the underlying language models, admitting that the agent sometimes “underestimates the complexity of work that is required to address certain issues.” For example, in one case, when failing to meet timing, Design Conductor tried to make major changes to "deepen the pipeline, instead of looking for simpler explanations." In another case, the researchers observed the model reasoning about Verilog, an event-driven language, as if it were sequential code. "While we found that this did not impact DC's ability to achieve functional correctness, it made it more challenging for DC to debug timing issues," the researchers explained. The researchers estimate that five to 10 human experts will still be required to guide the system toward a production-ready chip. In addition, compute requirements grow non-linearly as design complexity increases, which makes the whole process less practical on a commercial scale. Verkor said it plans to release VerCore's RTL source and build scripts by the end of April, and the company also intends to showcase an FPGA implementation at DAC (the annual Electronic Design Automation Conference). Previous AI chip design efforts, such as the Chinese researchers who produced a RISC-V CPU in under five hours in 2023 and the more recent QiMeng project , used different methodologies and architectures. Verkor’s Design Conductor handles the full design process from spec to GDSII autonomously, though it shares the same limitation that all other AI-designed chips have: no physical silicon.
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Reference reading
- https://www.tomshardware.com/tech-industry/artificial-intelligence/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/artificial-intelligence/ai-agent-designs-a-complete-risc-v-cpu-from-a-219-word-spec-in-just-12-hours#main
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