Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
rluker5 Wasn't Zen 4 4 wide, Zen 5 6 wide, and now Zen 6 will be 8 wide so on that, with 512 staying basically the same, the uplift could be less than from 4 to 5, or it could be more due to other things not clearly explained here. I'm skeptical of the ground up redesign though as I've heard that from AMD a few times before when it wasn't really true. It is definitely an improvement and the rumored 50% increase in cores per CCD will really help single CCD CPUs in some tasks, but the experience for most will likely be more dependent on clockspeed and IPC gains from the node change as the vast majority of common user tasks aren't significantly benefitted by using over 8 cores. If the node improvement isn't enough to offset the added heat from the added cores and wideness then sustained cockspeeds will be lower, as opposed to the rumors of 6, 6.5, 7.0 clocks. Heat comes from compute per second per area at a given efficiency. AMD is doing what they should with node improvements IMO as they are balancing the responsiveness of high clockspeeds with the inefficiency of high clockspeeds by using the improved efficiency of the node improvement to get more done per clock instead of going too far up the inefficiency curve. It isn't everything at once but getting the best practical outcome by balancing several related variables. It seems like AMD and Intel both do this and are both limited by node improvements (per core) and silicon expenditures (multicore, cache quantity) when it comes to CPU generational improvements. And a good example of where architectural design improvements outpaced node improvements is Rocket Lake. And a good example of going too far up the inefficiency curve on clockspeeds is Raptor Lake, especially when voltages were handled in some outdated archaic fashion with the built for Haswell LLC settings that were exacerbated by motherboard manufacturers giving a dirty all core undervolt at the expense of single core overvolt. I don't think many want to see Zen 6 repeat either of these mistakes and most would prefer an architecture and execution to best balance the opportunities and limitations given by the node and how much AMD is willing to spend on silicon per CPU. Don't hype yourself up too much from rumors and you won't be as disappointed with reality. The I/O die could bring some extra noticeable improvements though. Reply
jp7189 I'd like to hear more about the IOD. There should be some new tricks there to help feed the beast. Dare I hope for quad channel on the desktop? Bad timing with current memory prices. At the least, I expect the platform to be optimized for high RAM clockspeeds. Reply
George³ rluker5 said: Wasn't Zen 4 4 wide, Zen 5 6 wide, and now Zen 6 will be 8 wide so on that No, ZEN 5&6 have same front end 8 wide. Reply
Key considerations
- Investor positioning can change fast
- Volatility remains possible near catalysts
- Macro rates and liquidity can dominate flows
Reference reading
- https://www.tomshardware.com/pc-components/cpus/SPONSORED_LINK_URL
- https://www.tomshardware.com/pc-components/cpus/amd-pubs-first-zen-6-document-for-developers-a-brand-new-8-wide-cpu-core-with-strong-vector-capabilities#main
- https://www.tomshardware.com
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Informational only. No financial advice. Do your own research.