Intel, SK hynix shares surge following reports of chip packaging partnership — SK is said to be testing Intel's 2.5D EMIB for HBM integration
As for EMIB vs. CoWoS, they solve the same problem in opposite ways. CoWoS mounts every die on a large silicon interposer that all signals and power must cross, and the interposer scales with package size, so reticle-class designs waste silicon at the edges. EMIB, meanwhile, embeds small silicon bridges in the organic substrate only where two dies need to connect, with no interposer at all. Intel cites package utilization near 90% EMIB against roughly 60% for interposer-class packaging, because small bridges tile efficiently while large interposers don’t.
Bernstein analysts estimate EMIB packaging costs a few hundred dollars per chip against $900 to $1,000 for CoWoS on a Rubin-class processor, though the firm flags the fact that there’s a “ lack of an external production track record ” in that estimate. As always, there’s a trade-off: standard EMIB routes power around the bridge through the substrate in long, resistive paths. That might have been acceptable for Sapphire Rapids and Ponte Vecchio, but not for HBM4-class accelerators that draw more current.
EMIB-T closes that gap by adding through-silicon vias to the bridge die for vertical power delivery, and it’s set to enter production fab rollout this year . Intel has said EMIB-T supports HBM3, HBM3E, HBM4, and future HBM5 stacks and scales to a 120mm x 180mm package carrying more than 38 bridges and over 12 reticle-sized dies. Jaguar Shores, the successor to the canceled Falcon Shores accelerator, is the likely first product to use it.
Working with SK hynix could be a huge boon for Intel, with the qualification of its packaging by the South Korean memory giant potentially deciding whether it reaches flagship AI silicon or not. SK held a 57% share of HBM revenue in Q4 2025 per Counterpoint Research, and UBS expects it to take roughly 70% of the HBM4 supplied for Nvidia's Rubin platform this year.
HBM stacks are themselves a packaging problem: multiple memory dies bonded vertically through TSVs, then mounted next to a host processor with tight tolerances on power and thermal behavior. Validating those stacks on EMIB rather than a CoWoS interposer is the test of whether Intel can package memory to the standard Nvidia and Google require.
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An official thumbs-up from SK, or an HBM-4-on-EMIB-T production result, would convert Intel’s packaging from “tested” to “trusted.” But, until (or if) that happens, the split between accelerator types will remain: ASIC designers running lower memory bandwidth, including Google and Meta, can adopt EMIB sooner, while bandwidth-bound GPUs stay on CoWoS longer.
No named external AI customer is in EMIB or Foveros volume production today. Intel runs EMIB in its own server CPUs, including the 18A Clearwater Forest part whose 17-tile package uses 12 bridges, but every specifically named outside engagement so far, including Google’s order, points at 2027 or 2028 products or remains an evaluation.
Intel Foundry lost $10.3 billion on $17.8 billion of revenue in 2025, and in Q1 2026, the division posted $5.4 billion in revenue against a $2.4 billion operating loss, with external customers accounting for just $174 million of the total. CFO David Zinsner told the Morgan Stanley TMT conference in March that the foundry is close to closing deals worth "billions per year in terms of revenue" on advanced packaging alone, against a pipeline he had earlier measured in the hundreds of millions.
Another unknown is process yields: Intel uses 18A, its first node with gate-all-around transistors and backside power, for Panther Lake and Clearwater Forest, an internal proving ground before courting outside logic customers. However, Intel's most recent guidance is that yields are improving 7 to 8 percent each month, accelerated by enhanced cooperation with external partners.
Luke James is a freelance writer and journalist.\u00a0 Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory.\u00a0 ","collapsible":{"enabled":true,"maxHeight":250,"readMoreText":"Read more","readLessText":"Read less"}}), "https://slice.vanilla.futurecdn.net/13-4-24/js/authorBio.js"); } else { console.error('%c FTE ','background: #9306F9; color: #ffffff','no lazy slice hydration function available'); } Luke James Social Links Navigation Contributor Luke James is a freelance writer and journalist. Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory.
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