Intel's new space-grade Starfire chip is a Panther Lake SoC that puts an 18A CPU into orbit
Starting at the top of the core, the branch prediction area uses the existing Telum II design without any changes.
In the fetch engine, IBM leverages virtual cache tags to fetch data quickly with cache to avoid translation overhead.
IBM built automation tools to consume the ARM XML and understand how to move instructions through the core. IBM says this is the biggest area of silicon expansion in the core in order to support decoding AArch64 instructions.
In dispatch, IBM repurposed general purpose register rename in banked general registers 16 through 31.
In the arithmetic and load/store units, much of the major data flow is shared; addition is addition, as IBM put it. However, IBM implemented new hardware structures for SVE and special data types like FP16. IBM also says there was some non-obvious reuse of its existing CISC, such as memory copy and clear.
The X-Late, or translation, engine reuses the Translation Lookaside Buffer (TLB) but leverages a new page walk.
As opposed to a heterogeneous chip, which accomplishes mixing ISAs on the same die by leveraging different cores, IBM says the driving force behind a dual-ISA core was to deliver the scale of Arm software on a mission-critical platform. Mainframes are still the bedrock of vital data movement in financial institutions, governments, and more.
IBM generally ships new mainframes every two and a half to three years, with z17 mainframes revealed in 2024 at Hot Chips. We expect this mainframe to follow a similar timeline. As usual with deep mainframe infrastructure, however, the actual rollout largely depends on the institution's individual needs.
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TOPICS IBM See all comments (3) Jake Roach Social Links Navigation Senior Analyst, CPUs Jake Roach is the Senior CPU Analyst at Tom’s Hardware, writing reviews, news, and features about the latest consumer and workstation processors.
DS426 Yikes, can't wait to see that price tag with the accelerators going from LPDDR5 to HBM3e. Maybe Z18 mainframes will offer a bigger enough perf uplift to really consolidate on the number of mainframes needed? Guess that's already true in large part due to the new dual-ISA cores. Reply
Findecanor IBM is in the long game, for long-term customers. This is the latest in a long line since the System/360 in 1964 — 62 years ago. IBM already has its own RISC architecture in POWER/PowerPC (they merged back into one architecture some years back). I wonder if the choice of ARM was a technical decision, a political decision or a marketing decision. For one thing, Apple having transitioned Mac away from PowerPC to later focus on ARM might have tainted the POWER brand. Reply
usertests I've thought it would be interesting to sneak dual-ISA (separate cores) into x86 consumer chips. Like quad-core Cortex-A520++. Chiplets could make it easier. It does show up in some places, like the Pico 2. Reply
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