Intel's 5.7 GHz Xeon 6377P features 12 P-cores and a desktop-class LGA1700 socket
Intel centralizes all of the hardware for memory and I/O communication in the middle of the chip across two tiles (the fabric hubs), and each CBB can communicate with both fabric hubs.
Double-clicking into the diagram at the top of this section, you can see the layout of the I/O system above. Across the chip, Intel supports 128 lanes of PCIe 6.0, CXL 3.0, UPI 3, or some combination thereof, courtesy of the flexible I/O subsystem. Intel also includes four PCIe 4.0 lanes (a total of eight per CPU) for platform use.
The I/O fabric also includes complexes for the various accelerators on-chip in Diamond Rapids, including Intel QuickAssist Technology (QAT) and In-Memory Analytics Accelerator (IAA).
In the memory fabric, you can see the standard flow through the DDR PHY into the memory controller, but Intel includes some special sauce at the end of the chain, notably an on-die snoop filter. A snoop filter is a directory to maintain cache coherency, and moving it onto the CPU removes directory storage and cache coherency tasks from the memory.
Interestingly, Intel isn't leveraging its advanced EMIB packaging to connect the fabric hubs to the CBBs. Instead, Intel is using a standard UCIe-S connection through copper in the substrate. Intel says that UCIe-S offered a "low-latency uniform connection to all of the memory hubs" that "made the most sense for Diamond Rapids."
There were a handful of questions around UCIe-S versus an advanced packaging technique, UCIe-A. Intel says the choice mainly came down to distance, with UCIe-A requiring multiple "hops" depending on the distance. UCIe-S provides uniform access across longer distances, enabling lower latencies across the entire chip.
Although it's more of a footnote in the headline reveals about Diamond Rapids, the next-gen Xeon CPUs mark an important milestone in Intel's journey with AVX-512 and Intel's Advanced Performance Extensions, or APX, which has been described as a modernization of the x86 ISA. Both were described in 2023 , and now they're showing up in Diamond Rapids.
First, AVX. Expectedly, Diamond Rapids marks the move to AVX 10.2, which is supported on both P-cores and E-cores (AVX 10.1 only worked on P-cores). AVX 10.1 served as a transition step off of AVX-512 and only supported 512-bit vector instructions. AVX 10.2 supports converged 256-bit vectors, enabling execution on both P-cores and E-cores.
Diamond Rapids also supports Intel's APX. APX doubles the number of general-purpose registers from 16 to 32 with new encoding for registers 16 through 31. Intel says software will see a performance improvement when recompiled with APX, and without source code changes. We heard about APX support in Panther Cove nearly two years ago for the first time.
APX requires 10% fewer loads and 20% fewer stores in memory, according to Intel, and includes some key instruction updates like condition load and store. It doesn't require a code change, either, with full compatibility with previous code bases.
Between AVX 10.2, AMX, centralized I/O and memory communication, and 18A-P, Diamond Rapids brings forth a lot of innovation that Intel has been talking about for a long time. Whether it's too little, too late remains to be seen with the missteps around Granite Rapids.
Given the explosion of CPU demand for agentic workloads, Intel has a competitive part here that, at least, supports the latest updates to the x86 ISA and borrows a lot of key design points from AMD's evolution with EPYC. Intel has continued to double down on Coral Rapids; however, the generation that will follow Diamond Rapids will reintroduce SMT to Xeon.
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See all comments (0) Jake Roach Social Links Navigation Senior Analyst, CPUs Jake Roach is the Senior CPU Analyst at Tom’s Hardware, writing reviews, news, and features about the latest consumer and workstation processors.
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