As we see with all new process nodes, the nanometer-scale measurement doesn't coorelate to the physical dimensions of the device, but this remains a tremendous achievement.
Using two wafers for active transistor tiers instead of one could let IBM stack NFETs and PFETs vertically and optimize them independently, but such a method comes with a number of caveats that do not exist today with single-tier logic nodes.
The biggest issues are alignment and bonding yield, because two advanced logic wafers must line up with extreme precision, and any defect at the bond interface can kill the stack. Secondly, routing and power delivery could get more complex with two active device tiers. Thirdly, cooling gets harder now that one active tier sits farther from the heat sink. Last but not least are the costs. IBM has to pay for two advanced FEOL wafers, additional bonding and thinning steps, and manage higher process complexity and likely lower yields. As a result, the whole concept only makes sense if the density, SRAM, and performance-per-watt gains are large enough to offset manufacturing difficulties and cost penalty. IBM says nothing about costs and manufacturability, and the test chip it has completed is the size of a fingernail,' so not hard to make by today's standards. Meanwhile, it is highly likely that the approach only makes sense for heavy-duty data center AI solutions (which are near reticle size) and not for mainstream processors for client applications. For others, monolithic CFETs can do the job.
TSMC's details next-gen CoWoS roadmap: over 14-reticle packages and 48x leap in compute power expected by 2029
Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density
TSMC SoIC 3D stacking roadmap outlines path from 6-micron pitches today to 4.5-micron in 2029
On the bright side, IBM's 7A-class fabrication process does not rely on High-NA EUV lithography, as there are simply no such tools at the semiconductor research facility in Albany, New York, where IBM develops its technologies. Usage of proven Low-NA EUV systems makes it easier to get high yields now. Meanwhile, it remains to be seen how IBM's dual wafer approach works with High-NA EUV scanners that have half the exposure field compared to Low-NA EUV machines and therefore require field stitching, which does not really help yields. IBM implies that its next-generation nodes will use High-NA EUV lithography, so the company probably has ideas how to wed these new tools with its approaches to transistor designs.
When dealing with IBM's manufacturing technologies, one has to keep in mind that these are not fabrication processes that can be licensed and rapidly deployed at a high-volume fab, but are essentially a set of pre-competitive IPs, patents, and some R&D know-how that can be used to design an actual production node. For example, Rapidus licensed IBM's 2nm-class process, though it has yet to prove that it can create a competitive high-volume node.
IBM believes nanostack could make sense for sub-1nm generations and potentially enter mass production within the next five years.
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Anton Shilov is a contributing writer at Tom\u2019s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends. ","collapsible":{"enabled":true,"maxHeight":250,"readMoreText":"Read more","readLessText":"Read less"}}), "https://slice.vanilla.futurecdn.net/13-4-24/js/authorBio.js"); } else { console.error('%c FTE ','background: #9306F9; color: #ffffff','no lazy slice hydration function available'); } Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
usertests IBM has to pay for two advanced FEOL wafers, additional bonding and thinning steps, and manage higher process complexity and likely lower yields. As a result, the whole concept only makes sense if the density, SRAM, and performance-per-watt gains are large enough to offset manufacturing difficulties and cost penalty. Intel and others seem to be using crystal deposition and a single wafer to make CFETs. That seems to be superior, unless the optimizations achievable with two wafers are really important and can outweigh the cost for some chips. https://spectrum.ieee.org/cfet-intel-samsung-tsmchttps://spectrum.ieee.org/3d-cmos +40% higher SRAM density and doubled transistor density is nice, but going fully 3D SRAM may be better if you're resorting to stacking/bonding. Reply
dlheliski From the SEM the gate length is around 70nm, so calling it a 1nm process is a bit of a stretch … or maybe a shrink. Reply
nastastic dlheliski said: From the SEM the gate length is around 70nm, so calling it a 1nm process is a bit of a stretch … or maybe a shrink. The gate length cannot be determined from the image. The width of channel is along the x-axis (the ~70 nm you observe), the channel height is the y-axis. The length is along the z-axis in to/out of the image. Reply
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