Without any doubt, Micron will continue scaling 3D NAND along all three dimensions rather than simply increasing the number of layers going forward. While conventional 3D NAND scaling initially relied primarily on adding more memory layers, future generations will also require reductions in cell dimensions along the X and Y axes to improve bit density while keeping manufacturing complexity in check.
To achieve this, Micron is developing what it describes as breakthrough high-mobility materials, ultra-dense cell architectures, and more energy-efficient devices and data paths. These technologies could improve transistor characteristics, enable further reductions in memory cell dimensions, and reduce the energy required to move data within NAND devices.
"Beyond G11, we have a strong roadmap, not going to go into great detail on it today, but really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward," said DeBoer. "[…] The current industry direction and Micron’s direction is scaling both by adding layers [and] also by shrinking the cell dimensions."
The company has not disclosed specific architectural details, density targets, or production schedules for its post-G11 generations, though its roadmap suggests that future NAND scaling will increasingly depend on innovations in materials, cell architecture, and peripheral circuitry rather than layer-count increases alone. Meanwhile, since the number of active layers is arguably the easiest way to increase storage density, we would not expect the race towards the highest layer count to slow down substantially in the coming years, especially given strong demand for 3D NAND-based storage.
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Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
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