More importantly, the aforementioned tightening yield distribution improvements are said to be largely node-independent, which means they benefit multiple process technologies rather than the existing nodes, such as Intel 7/4/3. Indeed, there are many ways to reduce edge-related variability, and many of them are node independent, which means some of the methods developed at Intel should be applicable to 18A (though that isn't confirmed). In fact, one of the comments Intel made during its earnings call is that the yield curve of 18A progresses at a pace that is higher than expected.
"Lip-Bu had a [18A yield] target as we came into this year for the end of this year, and we are probably going to hit that probably the middle of this year," said David Zinsner, chief financial officer of Intel. "So, you know, he has done a very good job working the team to drive a better response there."
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Anton Shilov is a contributing writer at Tom\u2019s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends. ","collapsible":{"enabled":true,"maxHeight":250,"readMoreText":"Read more","readLessText":"Read less"}}), "https://slice.vanilla.futurecdn.net/13-4-22/js/authorBio.js"); } else { console.error('%c FTE ','background: #9306F9; color: #ffffff','no lazy slice hydration function available'); } Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
Findecanor When I first read "edge", I thought they meant better utilisation for packing rectangular chips on a circular wafer, so that the edges of the wafer aren't wasted. Or is there a specific reason why chips have to be laid out in grids? Reply
BillM12 Findecanor said: When I first read "edge", I thought they meant better utilisation for packing rectangular chips on a circular wafer, so that the edges of the wafer aren't wasted. Or is there a specific reason why chips have to be laid out in grids? In order to scribe and break a wafer into individual die, the wafer is laid out with common scribelanes in both directions. The scribe saw cuts across entire wafer in a straight line: but not through the entire wafer. To finish the cut, the wafer is gently shook to break it up So in effect, the wafer looks like straight roads that define rectangular "city blocks". The edge will lose die for several reasons: partial/incomplete die images, variable processing, etc. Any good processing will try to "center" and tighten the process window to optimize yields: this helps improve an entire wafer's yield as well improve performance. I'm shocked Intel had lost this basic silicon mfg discipline. Reply
evermorex76 BillM12 said: I'm shocked Intel had lost this basic silicon mfg discipline. I was going to say this makes it sound like they weren't bothering to try to improve yields past a certain point until they got desperate. I suppose efforts to do that had diminishing returns until the possibility of higher profits came into play, but they really make it sound like the new guy is doing something revolutionary by even trying, not just implementing new methods to go further. Reply
TerryLaze evermorex76 said: I was going to say this makes it sound like they weren't bothering to try to improve yields past a certain point until they got desperate. Desperate for what?!? This is about demand being so high that it makes this profitable, and/or ,this is about customers being so desperate that they buy anything. This article is still not at all clear about which one is happening. Intel doesn't need to be desperate to want to maximize profits, that's what they always try to do. Actually the better they do the better their ability to maximize profits. Reply
pjmelect Admin said: When I first read "edge", I thought they meant better utilisation for packing rectangular chips on a circular wafer, so that the edges of the wafer aren't wasted. I have often thought about this, why can’t the manufacturers make other smaller chips at the edges of the wafer so as to use more of the silicon? Reply
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- https://www.tomshardware.com/pc-components/cpus/more-details-emerge-about-how-intel-now-earns-more-revenue-from-each-wafer-by-looking-to-the-edges-analyst-reports-say-reduced-yield-variability-across-each-wafer-leads-to-more-sellable-cpus#main
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