Next-gen memory designed as a lower-cost, lower-power HBM alternative for AI workloads
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NEO Semiconductor announced on April 23rd that its 3D X-DRAM technology has successfully passed proof-of-concept (POC) validation, demonstrating that a new class of high-density DRAM can be manufactured using existing 3D NAND infrastructure. The company simultaneously announced a new strategic investment led by Stan Shih, founder and former Chairman and CEO of Acer, and a board director of TSMC for over two decades.
At the center of the announcement is the company’s 3D X-DRAM technology , a new class of DRAM that aims to break past conventional memory scaling limits by adopting a vertically stacked architecture designed for higher density, lower power consumption, and improved suitability for AI-driven workloads.
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"These results validate a new scaling path for DRAM," said Andy Hsu, Founder & CEO of NEO Semiconductor. "We believe this technology can enable significantly higher density, lower cost, and improved energy efficiency for the AI era. By leveraging established 3D NAND manufacturing processes and ecosystem, we aim to bring 3D DRAM to reality sooner. NEO is actively engaging with leading global memory and semiconductor companies on potential co-development opportunities, and we believe our technology is well suited for a scalable licensing and partnership model to bring next-generation AI memory solutions to market."
Industry commentary included in the announcement was quite positive — although this does not imply confirmation of viability at scale. TechInsights’ Jeongdong Choe described the results as a “significant milestone” in the shift toward 3D memory architectures, noting that conventional DRAM scaling is approaching physical limits and that the industry is increasingly exploring vertical alternatives.
The broader context behind this development is the growing strain AI workloads are placing on memory systems. While GPU compute performance has scaled aggressively over the past decade, memory bandwidth — the rate at which data can be fed to those processors — has become a limiting factor in large-scale AI training and inference systems. This has already driven widespread adoption of high-bandwidth memory (HBM), a vertically stacked DRAM architecture integrated close to GPUs. However, HBM presents complex 3D stacking and bonding requirements and high manufacturing costs.
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- https://www.tomshardware.com/tech-industry/artificial-intelligence/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/artificial-intelligence/neo-semiconductors-revolutionary-3d-x-dram-for-ai-processors-has-passed-proof-of-concept-validation-company-secures-funding-to-develop-next-gen-memory-hbm-alternative#main
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