Leading-edge foundry roadmaps for TSMC, Intel and Samsung — outlining the path to 1.4nm nodes and beyond
Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density
To break that trade-off, the consortium inverted the usual build order: rather than depositing metal onto the fragile film after the channel is in place, the team patterned tungsten-filled contact trenches first and transferred the 2D channel on top, with the gate deposited over it. Imec calls this a “reverse” thin-film-transistor flow, and credits the resulting bottom-contact geometry for the clean off-state behavior, in which both polarities stop conducting at zero gate voltage.
"For the first time, we achieved 50nm CPP — a metric determined by both the gate length and source/drain contact length — without affecting the performance of the 2D n and pFETs," said Gouri Sankar Kar, vice president of R&D for compute and memory device technologies at imec. The single-patterning EUV step, he added, was developed in close collaboration with ASML.
The 28nm channels and 50nm pitch were printed with one EUV exposure, well inside the resolution of standard 0.33-NA EUV scanners. ASML’s High-NA EUV work with imec targets far tighter pitches that would otherwise demand multi-patterning, but the 50nm pitch here needs neither High-NA tooling nor multiple exposures. ASML credited EUV's resolution for shrinking 2D channel lengths that earlier 300mm demonstrations had left large because they relied on older lithography.
Imec isn’t alone here, with Intel having run its own 300mm 2D-material program with the company, and Samsung having demonstrated wafer-scale growth of single-crystal MoS 2 . University groups have pushed monolayer MoS 2 transistors to gate pitches near the 1nm-node, but what sets imec’s work apart here is the combination of complementary n- and p-type integration, EUV single-patterning, and a node-relevant pitch on full 300mm tooling at once.
2D channels come after the complementary FET on most roadmaps, and it’s not just because of density. A TMD channel under a nanometer thick lets the gate control the channel more tightly than a silicon nanosheet several nanometers thick, which supports switching at lower voltage as gate lengths shrink.
Chinese fab SMIC's 7nm metal pitch beats Intel 18A but lags 38% on density, teardown finds
Analyzing TSMC's fab expansion roadmap — multi-fab N2 ramp, CoWoS, SoIC, and uncorking bottlenecks
TSMC unveils process technology roadmap through 2029 — A12, A13, N2U announced, A16 slips to 2027
Imec's long-range roadmap has placed 2D atomic channels beyond 2030, and IEEE Spectrum has reported that imec expects CFETs around 2033 and a switch to 2D-semiconductor channels closer to 2041, while the IRDS industry roadmap pencils in 2D channels as early as 2034 at the 0.7nm node, a timeline that sits well beyond today's silicon. TSMC only began volume production of its first gate-all-around node , N2, late last year, and the CFET that stacks n-type over p-type transistors is the next step before 2D channels become relevant to logic chips.
And while the demonstration is impressive, several challenges still separate it from a production process. First, the integration is quasi-CMOS: the n- and p-type materials are placed side by side by transferring films onto the wafer, not grown together in a single monolithic flow, and wafer-scale, residue-free transfer at production throughput remains unsolved. Beyond that, fab-compatible low-resistance contacts, controllable doping, and long-term reliability data all need to be addressed.
Dr. Min Cao, vice president and chief technology officer at TSMC, described the collaboration's aim as de-risking the lab-to-fab transition for novel channel materials. On the timelines imec and the IRDS have published, that transition is a 2030s problem at the earliest, and the first production role for 2D channels is likely to be modest back-end or wafer-backside devices, not high-performance logic. The engineering shown this week, however, narrows the work to be done down to manufacturing problems rather than questions about whether the devices can be built at pitch at all.
Follow Tom's Hardware on Google News , or add us as a preferred source , to get our latest news, analysis, & reviews in your feeds.
Luke James is a freelance writer and journalist.\u00a0 Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory.\u00a0 ","collapsible":{"enabled":true,"maxHeight":250,"readMoreText":"Read more","readLessText":"Read less"}}), "https://slice.vanilla.futurecdn.net/13-4-24/js/authorBio.js"); } else { console.error('%c FTE ','background: #9306F9; color: #ffffff','no lazy slice hydration function available'); } Luke James Social Links Navigation Contributor Luke James is a freelance writer and journalist. Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory.
Key considerations
- Investor positioning can change fast
- Volatility remains possible near catalysts
- Macro rates and liquidity can dominate flows
Reference reading
- https://www.tomshardware.com/tech-industry/semiconductors/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/semiconductors/imec-asml-and-tsmc-build-complementary-2d-material-transistors-at-50nm-pitch-on-a-300mm-wafer#main
- https://www.tomshardware.com/my-account
- Digital entrepreneur creates humorous 'physical NFT minting device' using a Raspberry Pi in quest for 'infinite money machine' — contraption trained on M3 MacBo
- First official details of AMD's next-gen 'Mustang Peak' Threadripper CPUs come into view — chips feature DDR5, PCIe 6.0, and a new socket
- SMI says Nvidia is driving its consumer PCIe 6.0 roadmap, not AMD and Intel — RTX Spark agentic AI platform fuels a hunger for storage bandwidth
- ASML denies US government report that its EUV chipmaking tool was shipped to China — says 'rumors' are 'inaccurate and damaging to our reputation'
- Coherent Breaks Ground on Expanded Texas Facility, Scaling AI’s Optical Backbone
Informational only. No financial advice. Do your own research.