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Qualcomm’s multiyear, cross-license deal with Huawei has a wide scope, covering 5G devices, AI services, near- and co-packaged optics and networks, a Huawei spokesperson told Bloomberg . Qualcomm also intends to purchase specific Huawei U.S. patents in compute, AI, networking, and other technologies, according to a release. Neither company’s announcement named any patents, LogicFolding, or any chip that uses it.
Bloomberg's report frames the deal as a win for Huawei, validating its chipmaking acumen. The deal remains subject to approval, and Qualcomm will reportedly pay Huawei to license its patents for the first time . According to the report, LogicFolding targets faster data transmission as a workaround for China’s lack of access to EUV lithography machines.
The Kirin 9050 Pro is used in the Huawei Mate XT 2 tri-fold smartphone, launched Sept. 7. Geekerwan, a Chinese tech review channel known for in-depth chip testing, had a lab slice the chip for its teardown. Kurnal, a semiconductor researcher who publishes die-shot analysis, also posted annotated shots of both dies on X. Geekerwan’s cross-section shows the two dies bonded face to face, and both show the execution units on top, with the PLLs also on the lower die.
Hisilicon Hi36E0(Kirin 9050) Dieshot
https://t.co/iKiY621Bmg https://t.co/qup0ANqYUE October 2, 2026
LogicFolding was first unveiled on May 25 by He Tingbo, president of Huawei’s semiconductor business, at IEEE ISCAS 2026 in Shanghai, under the company’s “Tau Scaling Law,” which uses signal delay rather than transistor size as a measure. Huawei describes both layers as active and working as one. Vertical interconnects work to create shorter signal paths, which can reduce energy consumption. Peking University’s “true 3D” design tool for the technology shows a 30% wire-length cut in its own tests.
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Huawei’s papers describe a “Kirin 2026” chip whose figures match the Kirin 9050 Pro’s. In a paper last month, relayed by TrendForce , Huawei said the chip uses a 1.5-micrometer hybrid-bonding pitch with about 50 million interconnects. About 10–15% of those carry signals. Core routing is 20% shorter, with critical paths up to 70% shorter. Power is reduced by as much as 66% for NPU, 58% for GPU, and 41% for a CPU performance core at the same performance level. NPU performance holds 29 TOPS at 63% less frequency and at a lower voltage.
Huawei does not name a process node. On its roadmap is Kirin 2027 at a 1-micrometer pitch and more than 100 million interconnects; for around three years out, a 720-nanometer pitch with over 200 million. It is targeting a 1.4nm-class density by 2031, with LogicFolding in the Ascend 990 AI accelerator around 2030. HiSilicon, Huawei’s chip-design unit, designs the Kirin chips, and SMIC is believed to make them, according to Reuters via TrendForce . It isn’t stated who handles the bonding process.
As for the Kirin 9050 Pro, Geekerwan tested it in a Mate 90 Pro Max phone. Analysis shows that the two dies are bonded with copper-to-copper hybrid bonding, metal layer to metal layer. The bonded circuit layers of both dies sit between two thick layers of silicon rather than directly on the package substrate. For the interconnects, about 80,000 through-silicon vias (TSVs) run through the lower die, taking up, with their keep-out zones, about 8% of the lower die’s usable area, Geekerwan says.
Watch On The split spans both dies. In the big CPU core, the execution units are on top, with the L1 and L2 caches directly beneath the load/store units, Geekerwan says. Kurnal's die shots put the GPU and NPU logic over their caches too. The lower die also holds a shared L3, a 12MiB system cache, PLLs, and the LPDDR, PCIe, camera, display, UFS, and USB interfaces, while the top die carries the ISP, modem, and memory controllers. Cache, I/O, and PLLs produce less heat and are less sensitive to the process, so they go below, Geekerwan explains; the denser compute goes on top, on a somewhat more advanced process.
Each die is just over 120 mm², which is smaller than the previous chip’s 140-plus mm². The total silicon area for both is therefore over 240 mm², up 70% overall. Density rose from 155 to 238 MTr/mm² at launch, about 53.5% higher, according to Huawei’s launch numbers. Other notable changes include the NPU’s area, up 150% across both dies, with Geekerwan measuring 68 TOPS INT8. The configuration makes sense and the rationale follows the layout, but an independent die analysis is needed for full understanding.
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Reference reading
- https://www.tomshardware.com/tech-industry/semiconductors/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/semiconductors/qualcomm-will-license-patents-behind-huaweis-logicfolding-chip-architecture-report-says-the-kirin-9050-pro-already-uses-it-with-a-teardown-showing-its-lower-die-is-mostly-cache-and-i-o#main
- https://www.tomshardware.com/my-account
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