Intel patent reveals new XBM memory architecture that ditches HBM's costly silicon interposer
Meanwhile, Intel's hybrid-bonding implementation, Foveros Direct, reached high volume with Clearwater Forest, the Xeon 6+ server processor built on the 18A node and demo’d at MWC back in March. The design uses a 9-micron copper-to-copper pitch to bond compute and I/O tiles onto base tiles that act as an active interposer, and Intel has described a second generation targeting a 3-micron pitch. Enabling that on a leading-edge logic node required a dedicated process variant, 18A-PT , which adds the through-silicon vias (TSVs) and bonding support that standard 18A doesn’t carry. The shift from Intel's earlier Foveros, which used solder microbumps across the Ponte Vecchio GPU's chiplets, to direct copper bonding is a generational change now playing out across its server offerings.
The widely held assumption was that HBM, the stacked DRAM that sits beside every AI accelerator, would be hybrid bonding's largest market by volume. That changed back in January when JEDEC raised the HBM package height limit from 720 to 775 microns, and the extra room means 16-high HBM4 stacks can be assembled with microbumps after all. With HBM4 pad pitch at 10 microns, reporting from SemiEngineering noted that moving to hybrid bonding at that pitch wouldn’t yet make economic sense.
SK hynix has reflected that logic in its own planning, reportedly sticking with advanced mass-reflow molded underfill for 16-high HBM4 while keeping hybrid bonding as a backup and continuing to validate 12-high hybrid-bonded samples for later generations. The company demonstrated a 16-layer HBM4 sample at CES 2026, built without the all-hybrid bonding many expected the generation to require. The result pushes hybrid bonding's HBM debut toward HBM4E and HBM5, expected around 2027 to the end of the decade, where taller stacks and tighter pitches finally make the older bonding methods run out of room.
Meanwhile, the memory makers are building the packaging capacity regardless. SK hynix is investing $3.87 billion in an advanced-packaging plant in Indiana, with production targeted for 2028, and Micron broke ground on a $7 billion HBM advanced-packaging facility in Singapore early last year, with output expected around 2027. Those plants are sized for the volumes hybrid bonding will eventually carry, even as the first HBM4 generation ships on the older interconnect, meaning the equipment commitments are running ahead of the technology's confirmed deployment date in memory.
Samsung is doing the same thing from the memory side. Its SAINT packaging family includes SAINT-D, which stacks DRAM directly on a logic die, and the company has discussed a bufferless HBM4 design that removes the separate base die, with custom HBM logic dies reportedly moving to its 2nm foundry process for 2027 samples. At GTC in March, Samsung claimed hybrid bonding cuts thermal resistance by more than 20% against thermocompression bonding.
Another drag on the timeline is intellectual property. Adeia, which holds a large portfolio of bonding patents, sued AMD last year, alleging that the hybrid bonding behind 3D V-Cache infringes 10 of its patents.
China is pursuing the technique as a way around its lack of access to cutting-edge lithography. With SMIC limited to 14nm-class production and cut off from next-gen EUV, domestic researchers have identified 3D hybrid bonding as a route to competitive performance by stacking older logic and DRAM, with public claims of 14nm parts paired with domestic DRAM aimed at rivaling far newer GPUs. Given that it’s China we’re talking about here, those claims remain claims, and no foundry has demonstrated mass production of hybrid-bonded logic memory in China.
In terms of tooling, Applied Materials and Besi, partners on hybrid-bonding equipment since 2020, launched their Kinex die-to-wafer bonding system late last year, billed as the first fully integrated die-to-wafer hybrid bonder combining surface preparation, bonding, and metrology. Applied Materials has taken an equity stake in Besi, and reports from March placed Besi at the center of takeover interest from both Lam Research and Applied Materials, an indication of how important the bonding-tool market has become as logic adoption ramps and memory adoption is staged behind it.
Analyst tracking put Besi’s hybrid-bonding revenue on a path toward roughly €476 million by 2026, up from about €36 million in 2023, with second-half 2025 orders rising more than 60% against the first half on early HBM4 production-line bookings. Competing tool vendors are moving in alongside it: ASMPT has partnered with EV Group on hybrid bonding, and SK hynix is working with Hanwha Semitech on bonders targeting a commercial HBM launch in 2027. The sheer scale of this equipment build-out is a clear demonstration that the industry is treating hybrid bonding as an inevitability, even where the products that’ll use it are still years out.
Hybrid bonding is already in volume production, but its capability is outpacing its adoption. TSMC offers 6-micron pitch while its newest disclosed customer ships at 9; Intel ships at 9 with 3 on the roadmap; and the memory market that was meant to consume it in quantity has bought itself one more generation on microbumps. Two things will show where it goes next — whether any leading logic product drops below 9 microns in volume, and whether HBM4E marks hybrid bonding's first real use in memory before the end of the decade.
Luke James Social Links Navigation Contributor Luke James is a freelance writer and journalist. Although his background is in legal, he has a personal interest in all things tech, especially hardware and microelectronics, and anything regulatory.
Key considerations
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Reference reading
- https://www.tomshardware.com/tech-industry/semiconductors/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/semiconductors/hybrid-bonding-roadmap-examined#main
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