What exactly the “it” Ho is referring to here remains a mystery, though given the context, it sounds like OpenAI may explore some way to productize its AI chip design workflow. Ho says Astra is a big step toward that, and we’ve already seen the model in action performing impressive feats, such as completing Portal autonomously .
Although OpenAI leveraged its own models heavily for Jalapeño's design and validation, it didn’t completely break the mold of traditional EDA workflows, particularly at the end of the design process. Before tapeout, tools from companies like Synopsys and Cadence perform a series of tests for signoff, including static timing analysis and signal integrity analysis. Ho says that OpenAI used this typical EDA flow for Jalapeño.
“But for sign-off, you need to use the standard EDA flows, and we did, because you want to make sure those results are good and correct. There’s no real alternative today. Part of it is this combination of standard flows optimized with AI, optimized by really good engineers,” Ho said.
OpenAI shared a multi-generational roadmap for accelerators. It says its second-gen ASIC is approaching tape-out, and its third generation is already in development. Although Ho said that the Jalapeño development cycle establishes a new baseline for chip design timelines, he was cautious about calling that cycle and cadence.
“Our projects and tape-outs will be dependent on the maturity level of the technologies. We can do very fast execution. Will we do those types of executions back-to-back? I doubt it, because the technology will not be ready for that, and I don’t want to tape out something that is 2% better than what I taped out before, because it’s not worth it to change a fleet,” Ho told us.
The executive was also clear that the Jalapeño timeline isn’t necessarily the same timeline all chips will follow. There were some “pragmatic trade-offs” in the early architecture design, with the team avoiding emerging, complex design points like 3D stacking and co-packaged optics. “Will it take longer? Will it take nine months? I won't say it will take nine months… but I think it will go faster than if you didn't have AI models.” You can read the full transcript of the interview, which covers a wide range of topics, at Tom's Hardware Premium.
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Jake Roach Social Links Navigation Senior Analyst, CPUs Jake Roach is the Senior CPU Analyst at Tom’s Hardware, writing reviews, news, and features about the latest consumer and workstation processors.
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Reference reading
- https://www.tomshardware.com/tech-industry/asics/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/asics/this-is-how-ai-should-be-used-openai-head-of-hardware-breaks-down-the-ai-assisted-design-of-its-jalapeno-asic#main
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