TSMC SoIC 3D stacking roadmap outlines path from 6-micron pitches today to 4.5-micron in 2029 — Fujitsu’s Monaka CPU to benefit from face-to-face chiplet stacki

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TSMC SoIC 3D stacking roadmap outlines path from 6-micron pitches today to 4.5-micron in 2029 — Fujitsu's Monaka CPU to benefit from face-to-face chiplet stacki

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TSMC's 3D stacking SoIC technology has always been somewhat of a backburner project for TSMC, as it gained support for new process technologies slowly, when compared to CoWoS. From a pure interconnection pitch point of view, TSMC offered a rather fine 9 µm pitch in 2023, which was good enough to enable products like AMD's Instinct MI300-series . However, the 1 st generation SoIC had one major limitation: it only supported face-to-back (F2B) stacking, but not face-to-face (F2F) stacking, which is supported by the 2 nd generation SoIC technology. In 2025, TSMC achieved 6 µm pitches and expects the pitch size to decrease to 4.5 µm by 2029.

Face-to-back stacking imposes fundamental limits because signals cannot travel directly between dies. Instead, they must cross multiple metal layers and pass across through silicon vias (TSVs) in the bottom die, which increases latency, power consumption, and routing complexity.

You may like TSMC's details next-gen CoWoS roadmap: over 14-reticle packages and 48x leap in compute power expected by 2029 Why TSMC grew four times faster than its foundry rivals in 2025 Intel's EMIB-T packaging technology set for fab rollout this year In addition, this limits how densely connections can be implemented, since TSVs are relatively large structures that cannot be placed at fine pitch across active logic regions without affecting transistor density and design considerations. According to Broadcom, a real-world design using face-to-back stacking can achieve 1,500 signals/mm 2 with TSVs.

By contrast, face-to-face stacking removes the indirect signal path by aligning the metal layers of two dies directly and connecting them using hybrid copper bonding. This enables straight, ultra-short vertical interconnects without relying on TSVs, which increases signal density by an order of magnitude to 14,000 signals/mm 2 , which therefore increases bandwidth, reduces latency, and cuts energy usage per bit.

As a result, communication between stacked dies resembles on-die wiring rather than chip-to-chip links, which is why companies like Broadcom view it as a crucial capability to scale compute density for next-generation AI and HPC processors .

Now that TSMC can do both F2F and F2B stacking, development of the technology will proceed much faster than before. The company now touts the usage of N3P dies on top of N4 dies, expects N2P on top of N3P within the next year, N2P on top of N2P by 2028, and envisions 3D stacked A14 dies by 2029.

Notably, the company hasn't demonstrated any process technologies with a backside power delivery in its SoIC roadmap. Yet, TSMC SVP Kevin Zhang reassured us that these nodes can support 3D integration as well.

"That may just be a simplification in the slide, A16 will have stacking capability," said Kevin Zhang, TSMC's Senior Vice President of Business Development and Global Sales, and Deputy COO.

"The SoIC roadmap shown does not cover all possible combinations — there are many permutations. The key takeaways are twofold. First, pitch scaling — from 9 µm to 6 µm, and eventually down to 4.5 µm. Second, the acceleration of stacking timelines. In the past, for example, you might stack N3P on N4, since the base die with TSV takes time to mature — 3nm TSV is only expected around 2027. But looking ahead to 2029, A14 TSV becomes available just one year after initial production. That shows how we are accelerating the schedule, enabling customers to stack the most advanced dies on top of each other much sooner."

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