Synopsys validates a PCIe 6.0 PHY inside a face-to-face 3D stack at 64 GT/s — says it got there by pulling apart an existing 2D test chip

In monolithic chips, PCIe PHYs sit at the perimeter of the die, right next to the package I/O connections, helping keep traces to the substrate short so attenuation and reflections remain manageable. A 2.5D package prese…

CXMT planned to use stolen Samsung IP to develop its DRAM, court hears — former Samsung engineer who jumped to Chinese memory maker now behind bars

The intention was a key part of CXMT’s business plan rather than an opportunistic attempt to acquire Samsung’s technology after the start of its own DRAM process development, according to the testimony of a former Samsun…

Unlock Tom’s Hardware Premium’s Hot Chips 2026 coverage for free — sign up for an account to read technical breakdowns from the show

Bolstering this are Premium Roadmaps , which cover a vast swathe of topics, all the way from the newest enterprise GPUs to roadmaps for Co-Packaged Optics technologies, and TSMC’s own fab expansion plans, to give you a w…