It’s not double the cache of the 9950X3D, however, just double the amount of stacked cache. Each Zen 5 CCD has 32 MB of L3 cache, so the 9950X, for example, has 64 MB of L3 total. The 9950X3D boosts that to 128 MB by stacking an additional 64 MB under one CCD. Here, we have the extra 64 MB under both CCDs for a total of 192 MB of L3.
Particularly in heavily-threaded tasks, the goal it seems is to keep data close to the cores. For the other eight cores that otherwise wouldn’t have access to the large, shared pool of L3, they now don’t need to cross over to other CCD to get the data they need. That’s the idea, at least.
Adding extra cache comes with downsides, particularly in thermal and power demands. The Ryzen 9 9950X3D2 peaks slightly lower than its single-cache counterpart at 5.6 GHz, and it demands a 200W TDP, with a peak platform power of 270W; the highest of any consumer Zen 5 CPU. You still get the same 16 Zen 5 cores and 32 threads as the Ryzen 9 9950X3D and Ryzen 9 9950X, however.
The haircut in peak clock speed is telling here, suggesting that a dual cache X3D part wouldn’t have been possible with the previous Zen 4 design. AMD previously stacked the cache on top of the CCD, insulating the cores from direct access to the IHS. Now, the extra cache is under the CCD. That not only allows the Ryzen 9 9950X3D2 to maintain a high-end thermal design, but also to offer full overclocking support, alongside AMD’s Precision Boost Overdrive (PBO).
The Ryzen 9 9950X3D2 is the first 3D V-Cache CPU to have stacked L3 cache on both CCDs. The natural question: Does that actually matter? More cache is more cache, but the additional stack here seems like it has less to do with capacity and more to do with latency. As mentioned, if you can access data from L3 on CCD 2, that means you don’t need to go over to CCD 1, which creates additional latency.
First, let’s establish that’s actually the case. Above, you can see a core-to-core heatmap for the Ryzen 9 9950X3D2. This is all about core-to-core communication, and it’s just an illustration to establish that, yes, there’s an additional latency penalty when a core has to cross over to the other CCD. So, if core 16 on CCD 2 needs to get data from the L3 stored on CCD 1, there’s an additional latency hit.
Now, we can look at our latency testing, which measures the time in nanoseconds when allocating different region sizes. Both the Ryzen 9 9950X3D and the non-X3D model see a big increase in latency past about 32 MB, which is the amount of L3 that’s actually on the CCD (the extra 64 MB is stacked for the Ryzen 9 9950X3D). The Ryzen 9 9950X3D2 extends that further, to around 64 MB.
This doesn’t translate directly into better performance, mind you. Lower latency is better performance, but we’re already looking at a truncated version of this chart, starting with a 64 KB region size. The benefits show up when you’re pushing past that normal 32 MB L3 chunk on a Zen 5 CCD.
Jake Roach is the Senior CPU Analyst at Tom\u2019s Hardware, writing reviews, news, and features about the latest consumer and workstation processors. ","collapsible":{"enabled":true,"maxHeight":250,"readMoreText":"Read more","readLessText":"Read less"}}), "https://slice.vanilla.futurecdn.net/13-4-20/js/authorBio.js"); } else { console.error('%c FTE ','background: #9306F9; color: #ffffff','no lazy slice hydration function available'); } Jake Roach Social Links Navigation Senior Analyst, CPUs Jake Roach is the Senior CPU Analyst at Tom’s Hardware, writing reviews, news, and features about the latest consumer and workstation processors.
Gururu How was it decided to find a bunch of obscure benchmarks that are rarely used in CPU testing? Seems like a little voice whispered in someone's ear… Reply
Marlin1975 Seems like a chip that with the right software will be a beast. I'm assuming since most is not written for this much cache its left spinning its wheels when it has more to go. Reply
yznc Admin said: The Ryzen 9 9950X3D2 is one of the most unique CPUs we’ve ever reviewed, and although its price feels like a kick in the gut, it offers some interesting, highly specialized improvements in certain workloads based on our testing. AMD Ryzen 9 9950X3D2 review: More cache, more cash : Read more Very nice and informative article! Can I get a clean pdf version for education use? Thank you! Reply
JakeRoach Gururu said: How was it decided to find a bunch of obscure benchmarks that are rarely used in CPU testing? Seems like a little voice whispered in someone's ear… It's the same list of benchmarks we use in every review, AMD and Intel. Reply
Gururu JakeRoach said: It's the same list of benchmarks we use in every review, AMD and Intel. Yes, I don't see anything wrong. It's just a little confusing on the SPECWorkstation 4 Benchmarks where if you compare the 270K review to this review, some tests seem different. Maybe they are just listed in a different order. Reply
TerryLaze Marlin1975 said: Seems like a chip that with the right software will be a beast. I'm assuming since most is not written for this much cache its left spinning its wheels when it has more to go. Cache is completely transparent (invisible) to apps, they either have enough data to fill the cache or they don't. You would need to invent an app that causes the problem of needing that much cache for it to use that much cache. (Which is what a lot of the benchmarks do, they use a lot more data (or at least coherent/fixed amount of data that never needs to change) than what a normal real world usage would be) Reply
zworykin Not "one of the most unique" CPUs you've reviewed. It's unique, or it isn't. There are no degrees of "more unique" or "less unique" – it's a binary concept. Reply
drea.drechsler "A terrible value, but one of the most unique… isn’t worth the money for the vast majority of people, but it was never meant to be. It’s a halo product….. one of the most unique …. ever reviewed, and although its price feels like a kick in the gut… . " Sounds like summary statements appropriate to an Nvidia GPU reviews. Reply
qxp TerryLaze said: Cache is completely transparent (invisible) to apps, they either have enough data to fill the cache or they don't. You would need to invent an app that causes the problem of needing that much cache for it to use that much cache. (Which is what a lot of the benchmarks do, they use a lot more data (or at least coherent/fixed amount of data that never needs to change) than what a normal real world usage would be) No need to invent anything. If you just consider an app that at its core does FFT or vector arithmetic then as soon as the size of the data is larger than cache of 9950 but smaller than 9950X3D2 you will see a big difference in speed. The reason you don't quite see this in charts of this article is because most apps are in two categories – either they are written without much attention to performance, in which case they spend most time in CPU executing some byte code or inefficient loops and the extra cache does not matter. Or they have been well optimized and part of that optimization was to fit them into the cache of the CPUs they were designed for, and the case of my data is larger than cache was treated as a slow path. Reply
bit_user Thanks for the comprehensive benchmarks! I had always wondered how such a product would perform – now I know! In your intro, I didn't notice a reference to why AMD said they didn't offer this before. I'd have to go searching for it, but they've previously said they didn't think it would be cost-effective. It seems they were right. I'm glad to see very few regressions vs. the 9950X and 9950X3D, however. That means it's a safe buy for someone who wants the top AM5 multithreaded performer, if money is no object. Reply
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