Hassam Nasir is a die-hard hardware enthusiast with years of experience as a tech editor and writer, focusing on detailed CPU comparisons and general hardware news. When he\u2019s not working, you\u2019ll find him bending tubes for his ever-evolving custom water-loop gaming rig or benchmarking the latest CPUs and GPUs just for fun. ","collapsible":{"enabled":true,"maxHeight":250,"readMoreText":"Read more","readLessText":"Read less"}}), "https://slice.vanilla.futurecdn.net/13-4-25/js/authorBio.js"); } else { console.error('%c FTE ','background: #9306F9; color: #ffffff','no lazy slice hydration function available'); } Hassam Nasir Social Links Navigation Contributing Writer Hassam Nasir is a die-hard hardware enthusiast with years of experience as a tech editor and writer, focusing on detailed CPU comparisons and general hardware news. When he’s not working, you’ll find him bending tubes for his ever-evolving custom water-loop gaming rig or benchmarking the latest CPUs and GPUs just for fun.
usertests 2.0 GHz is still lasted as the base frequency listed Note: 10-core Medusa Point is considered to be an 8-core Krackan Point successor. We're looking at gains with Zen 6 that are similar to Zen 4, from a decent IPC uplift and higher clocks. Apparently up to 5.37 GHz turbo on this part, only a little higher than the 5.1-5.2 GHz seen this generation from Krackan/Strix/Gorgon, but I think sustained all-core clocks are likely doing much better due to efficiency improvements. Is "cluster" analogous to CCX in Geekbench listings? I think it's probably one 10-core CCX here. If 32 MiB L3 cache is accurate that will be a doubling from Krackan, very nice. I guess this SKU will have 8 CUs of RDNA4m, but no confirmation seen anywhere yet. Strix Point was often bandwidth starved, so 8 CUs of RDNA4m may perform much better than you would expect, also with full fat/speed FSR4 support. Krackan looked nice to me when it was available in $400-500 laptops (not anymore, but I see a good recent but expired deal). Medusa Point will be a great improvement, softening the blow of the terrible pricing. Reply
thestryker I've been thinking about the cache configurations since the first leaks as 32MB doesn't really make sense. My assumption has been that the regular mobile cores may just have half of what desktop does leading to 24MB. Historically the C cores have halved regular cores which would drop that to 12MB. Obviously 24 + 12 isn't 32 so that would mean one of two things to me: the C cores are sharing 8MB or AMD has improved the way they're disabling cache and are doing it in 4MB chunks instead of the 8MB with Zen 4/5. As for the performance I'd point out that the 9600X has presumably the same boost clock as this sample being tested. Reply
usertests thestryker said: I've been thinking about the cache configurations since the first leaks as 32MB doesn't really make sense. My assumption has been that the regular mobile cores may just have half of what desktop does leading to 24MB. Historically the C cores have halved regular cores which would drop that to 12MB. Obviously 24 + 12 isn't 32 so that would mean one of two things to me: the C cores are sharing 8MB or AMD has improved the way they're disabling cache and are doing it in 4MB chunks instead of the 8MB with Zen 4/5. We should be looking at 4x Zen 6 + 4x Zen 6c + 2x Zen 6 LP. If you extrapolate from Krackan and assume a 50% across the board increase in L3 cache for Zen 6 products, you get to 24 MiB. That's ignoring the two LP cores. We have no examples yet of how AMD will treat LP cores, but I guess you can assume zero L3 for now. Maybe these LP cores are in a separate CCX, but it's a monolithic die and we will see 12-core CCXs this generation. 32 MiB unified would be a crazy improvement when Krackan had 16 and Strix Point had the 16 + 8 split. It's safe to assume misdetection for now. Reply
thestryker usertests said: 32 MiB unified would be a crazy improvement when Krackan had 16 and Strix Point had the 16 + 8 split. I haven't seen any shots of Krackan showing the core design so I don't know if it's similar to Strix or Phoenix. With Phoenix the regular and C cores directly shared the cache so I suppose that would be another option where it's just a single shared cache rather than split. usertests said: Maybe these LP cores are in a separate CCX It makes sense that they'd be separated in some fashion as that's what Intel has done with all of theirs even when on the same silicon. Reply
usertests usertests said: If you extrapolate from Krackan and assume a 50% across the board increase in L3 cache for Zen 6 products, you get to 24 MiB. That might not be a great assumption since budget APUs should be on an N3 node while desktop CCDs are on an N2 node with denser SRAM. But who knows. Reply
Thunder64 usertests said: We should be looking at 4x Zen 6 + 4x Zen 6c + 2x Zen 6 LP. If you extrapolate from Krackan and assume a 50% across the board increase in L3 cache for Zen 6 products, you get to 24 MiB. That's ignoring the two LP cores. We have no examples yet of how AMD will treat LP cores, but I guess you can assume zero L3 for now. Maybe these LP cores are in a separate CCX, but it's a monolithic die and we will see 12-core CCXs this generation. 32 MiB unified would be a crazy improvement when Krackan had 16 and Strix Point had the 16 + 8 split. It's safe to assume misdetection for now. I thought the rumor was the LP cores were on the IOD? That seems to make sense. Reply
usertests Thunder64 said: I thought the rumor was the LP cores were on the IOD? That seems to make sense. This product should be monolithic, and even for the Zen 6 APUs that are not monolithic, they supposedly have an IOD/central chiplet that has all 3 types of cores and the iGPU. They can optionally have a desktop chiplet added to boost the core count. It's the desktop CPUs that have physical separation of LP cores on the IOD, but only if AMD commits to it. We've also seen a leaker claim the iGPU will be dropped in favor of an NPU! So Olympic Ridge details are up in the air for now. Reply
JamesJones44 In fact, the single-core result is better than any mobile part on Geekbench apart from the new Snapdragon X2 Elite lineup Also apart from the Apple Silicon lineup. The base M5 has a single core score of 4223 and multi-core score of 17475 Reply
Key considerations
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Reference reading
- https://www.tomshardware.com/pc-components/cpus/SPONSORED_LINK_URL
- https://www.tomshardware.com/pc-components/cpus/amds-next-gen-10-core-medusa-point-apu-shows-up-on-geekbench-again-with-its-best-score-yet-leaked-sku-outpaces-every-other-x86-mobile-chip-in-the-single-core-test#main
- https://www.tomshardware.com/subscription
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