usertests This is a positive development, but from a previous leak, the budget bLLC SKUs could feature less L3 cache, similar to most other Intel CPUs tying cache slices to cores/clusters. So AMD could put out a budget X3D CPU with 8-10 cores and the full 144 MiB, while Intel's version has 108 MiB. I think it's 12 MiB per P-core or E-core cluster, so 108 MiB for 6P + 12E. Edit, it was also a Jaykihn leak: https://videocardz.com/newz/intel-core-ultra-400d-400dx-nova-lake-s-skus-to-feature-up-to-288mb-of-cache Technically, it's 24 MiB per two P-cores, since Jaykihn is claiming those are clustered with shared 4 MiB L2 cache: https://www.tweaktown.com/news/111118/intels-nova-lake-will-unify-l2-cache-and-feature-new-d-and-dx-lines-for-enthusiasts-claims-leaker/index.html Reply
Gururu So we already know that the bLLC is best with high end GPUs. Has anything been demonstrated that the 5080/5090 only can utilize a certain amount, or is it always a case that these and faster GPUs to come will always use as much as they are given? Reply
usertests Gururu said: So we already know that the bLLC is best with high end GPUs. Has anything been demonstrated that the 5080/5090 only can utilize a certain amount, or is it always a case that these and faster GPUs to come will always use as much as they are given? L3 cache in the CPU is utilized by the CPU, not GPU. If it lifts a CPU bottleneck too high then you'll need a high-end GPU like 5090 to get the higher FPS. However, there can be subtle benefits that don't need the fast GPU, like higher 1% lows, or better power efficiency. Some types of games tend to get an outsized benefit, like simulation titles. Then there are professional workloads that will benefit from big L3 cache, but not too many. Most reviewers don't have test suites large enough to identify these, so you have to go to the GOAT… Michael Larabel at Phoronix. Reply
TerryLaze usertests said: L3 cache in the CPU is utilized by the CPU, not GPU. If it lifts a CPU bottleneck too high then you'll need a high-end GPU like 5090 to get the higher FPS. However, there can be subtle benefits that don't need the fast GPU, like higher 1% lows, or better power efficiency. Some types of games tend to get an outsized benefit, like simulation titles. Then there are professional workloads that will benefit from big L3 cache, but not too many. Most reviewers don't have test suites large enough to identify these, so you have to go to the GOAT… Michael Larabel at Phoronix. His point was "is there really going to be any difference between 108-144Mb" … Once you have a big enough cache for your cores (or his point for the game since that is what the GPU is displaying) are the benefits still increasing. Did anybody do any testing on a x3d cpu limiting the cache in say 10mb steps? Reply
usertests TerryLaze said: His point was "is there really going to be any difference between 108-144Mb" … Once you have a big enough cache for your cores (or his point for the game since that is what the GPU is displaying) are the benefits still increasing. Did anybody do any testing on a x3d cpu limiting the cache in say 10mb steps? There are clearly diminishing returns, already seen by moving from 32 MiB to 96 MiB, and it's highly game-specific. Average uplift from tripling your L3 cache is what, 15%? It was more like 30% in Tom's 9800X3D review but that is probably on the high side and for 1080p. There will be games that "tap out" the amount they can use between 32-96, or 96-144. If anyone has done that step testing, I haven't seen it. But there will suddenly be a large variety of different cache levels available to compare in the coming generations: 32 MiB Zen 3/4/5 CCD 36 MiB Raptor/Nova Lake 8P + 16E 48 MiB Zen 6 CCD 64 MiB Zen 7 CCD (16-core) 96 MiB Zen 3/4/5 X3D 108 MiB Nova Lake bLLC 6P+12E 132 MiB Nova Lake bLLC 8P+12E 144 MiB Zen 6 X3D, Nova Lake bLLC 8P+16E 224 MiB Zen 7 X3D Notably, 48/64 from AMD filling that big gap we've had, 108/132 from Intel filling the new gap, and Zen 7 X3D delivering a stupidly high amount of L3 cache. (Dual variants can hit 192/288/448 total, but are unlikely to be exploited by game engines anytime soon.) Reply
cp0x I am planning to build a high end 52-core gaming machine using this CPU and 4GB of RAM (or even 8GB RAM if I get a raise and a large tax refund and I manage to save up enough money by then). I should be able to afford a 3060 GPU by then. Welcome to 2027. Reply
rluker5 usertests said: There are clearly diminishing returns, already seen by moving from 32 MiB to 96 MiB, and it's highly game-specific. Average uplift from tripling your L3 cache is what, 15%? It was more like 30% in Tom's 9800X3D review but that is probably on the high side and for 1080p. There will be games that "tap out" the amount they can use between 32-96, or 96-144. If anyone has done that step testing, I haven't seen it. But there will suddenly be a large variety of different cache levels available to compare in the coming generations: 32 MiB Zen 3/4/5 CCD 36 MiB Raptor/Nova Lake 8P + 16E 48 MiB Zen 6 CCD 64 MiB Zen 7 CCD (16-core) 96 MiB Zen 3/4/5 X3D 108 MiB Nova Lake bLLC 6P+12E 132 MiB Nova Lake bLLC 8P+12E 144 MiB Zen 6 X3D, Nova Lake bLLC 8P+16E 224 MiB Zen 7 X3D Notably, 48/64 from AMD filling that big gap we've had, 108/132 from Intel filling the new gap, and Zen 7 X3D delivering a stupidly high amount of L3 cache. (Dual variants can hit 192/288/448 total, but are unlikely to be exploited by game engines anytime soon.) I like where you are going with this. As far as I know only Intel will limit the cache on cut down SKUs, but doesn't necessarily have to. If you can disable cores and not cache on the higher SKUs then maybe we can get a real apples to apples comparison (like they did with Skylake arch SKUs with varying cache) of 6p+12e from base, disabled 8p+12e, disabled 8p+16e, bllc 6p+12e, bllc,d 8p+12e, bllc,d 8p+16e. Which would give steps of 27, 33, 36, 108, 132, 144MB (with 6p+12e at same clocks)if my arithmetic is correct. Still leaves a giant hole between 36 and 108MB, but at least there are nice steps above 108. All it will take is for some reviewer to buy all of those CPUs and run the tests. It would be really nice if there were a way for a dual compute chip NVL, with the compute cores on one disabled, for the enabled cores to use the cache on the disabled cores chiplet as another level between it's cache and ram, but I believe that takes extra hardware resources to do which NVL wouldn't have. Reply
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