As expected, the slide re-confirms that the upcoming 5 th Generation inference accelerator called SI5 (aka HW5 aka AI5) will be manufactured using 3nm- and 2nm-class process technologies at TSMC and Samsung Foundry, respectively, and will adopt a multi-chip module (MCM) design, marking a departure from the conventional packaging approach used for HW4. Tesla expects SI5 to deliver a 40X performance improvement over HW4, which will be a result of an eightfold increase in compute capabilities (driven by considerably denser process technologies and more execution units) and a fivefold gain from silicon optimization, according to Elon Musk, which points to 8,640 – 23,040 TOPS (an estimated figure), depending on how one counts performance of HW4. Meanwhile, the processor is expected to consume from 250W to 800W depending on application, so making performance estimates at this point is not exactly a good business. Meanwhile, the processor will also feature six times more memory than its predecessor (i.e., 96 GB). Depending on the memory type used (GDDR6 or GDDR7), the Tesla SI5 can offer memory bandwidth between 768 GB/s and 1.536 GB/s.
Moving on to the Tesla's 6 th Generation inference accelerator (SI6), which is set to further increase compute performance to 80 times that of HW4 and feature eight times more memory than the current-generation processor. This could translate to 17.28 – 46.08 POPS (quadrillion operations per second), depending on how to count HW4 performance, and 144 GB of memory, which is significant performance and amount of memory for an AI accelerator.
Tesla has already inked a deal with Samsung Foundry to make its 6 th Generation inference accelerators through 2033, and the new slide reveals that the unit will be made using a 2nm-class process technology. Given the fact that the chip is due in 2029 – 2030 and Samsung's recently updated foundry roadmap , we are probably talking about automotive-grade SF2A, performance-enhanced SF2P, or even SF2Z with backside power delivery. Meanwhile, a thing that strikes the eye with the SI6 is that Tesla does not envision the chip to be produced at Terafab using Intel's 14A fabrication process in the 2030s.
SI6 will retain the multi-chip module (MCM) approach introduced with AI5/SI5/HW5 , which seems rational as it will be able to leverage experience it is going to get with its 5 th Generation inference accelerator and retain relatively reasonable packaging costs. Many automakers are considering adoption of multi-chiplet designs and HBM memory for their next-generation system-in-packages (SiPs), which will drive their costs. It remains to be seen when Tesla adopts HBM for its inference accelerators, but probably not with SI6.
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Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
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