Speaking of customer design readiness, Wei indicated that clients strive to tape-out their A14 designs ahead of schedule, which is a good sign. It is also interesting to note that despite the fact that A14 lacks Super Power Rail backside power delivery (A12 will gain SPR in 2H 2019), it is set to be adopted not only by client processors, but also by AI/HPC applications.
"We are observing a strong level of customer interest and engagement on both smartphone and HPC/AI applications, and customer new tap-out activity is ongoing and ahead of schedule," Wei said.
A14 is TSMC's next-generation process technology that combines the company's 2nd Generation GAA nanosheet transistors with a new standard-cell architecture to improve performance, power efficiency, and transistor density. Compared with N2, TSMC expects A14 to deliver a 10% – 15% performance uplift at the same power and transistor count, or reduce power consumption by 25%–30% at the same frequency and complexity. The node is also projected to increase transistor density by around 20% for mixed designs and by 23% for logic.
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Anton Shilov is a contributing writer at Tom\u2019s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends. ","collapsible":{"enabled":true,"maxHeight":250,"readMoreText":"Read more","readLessText":"Read less"}}), "https://slice.vanilla.futurecdn.net/13-4-25/js/authorBio.js"); } else { console.error('%c FTE ','background: #9306F9; color: #ffffff','no lazy slice hydration function available'); } Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
usertests The node is also projected to increase transistor density by around 20% for mixed designs and by 23% for logic. I've said it before but it seems like they are getting a decent (>=13%) SRAM density increase at this node, which is always good to see. The death of SRAM scaling was mildly exaggerated. It is also interesting to note that despite the fact that A14 lacks Super Power Rail backside power delivery (A12 will gain SPR in 2H 2019), it is set to be adopted not only by client processors, but also by AI/HPC applications. I hope backside power delivery becomes a standard feature for most chips eventually. I think it's almost a half-node jump applied to any particular node, so it could be inevitable. Reply
DS426 N2, A14, and A12 were talked about in this article but what about A16? I realize TH has a recent article on TSMC saying A16 is slipping back to 2027, but comparisons to A16 could have been made. It's notable because A16 does have backside power delivery, which is a TSMC first and might explain a big reason why A16 is behind schedule and yet A14 is ahead of schedule as it's missing it. Reply
attimony DS426 said: N2, A14, and A12 were talked about in this article but what about A16? I realize TH has a recent article on TSMC saying A16 is slipping back to 2027, but comparisons to A16 could have been made. It's notable because A16 does have backside power delivery, which is a TSMC first and might explain a big reason why A16 is behind schedule and yet A14 is ahead of schedule as it's missing it. BSPDN is too expensive (because bonded two wafer)so there is few or no customer Reply
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