Hot Chips 2026: Nvidia touts benefits of its DSX MaxLPS site power management approach — tech allows for more compute from fixed data center power budgets

At the rack level, DSX MaxLPS offers further flexibility through workload-specific power profiles. Much like the quiet, balanced, and high-performance power modes that client PC users are familiar with, Nvidia has produc…

Hot Chips 2026: Nvidia breaks down 88-core Vera CPU — spatial multithreading benchmarked, 1.2 TB/s SOCAMM2 memory, agentic workloads detailed, and more

Nvidia’s slide does a good job illustrating, but it’s worth noting the difference compared to traditional SMT nonetheless. With traditional SMT, resources are time-sliced between threads, leading to gaps between BP and d…

Hot Chips 2026: High Bandwidth Flash promises massive bandwidth and capacity, but its usability is extremely limited — new memory format strikes a balance betwe

Additionally, more local capacity could also reduce communication between accelerators. Conventional expert parallelism distributes experts across GPUs and requires all-to-all communication at every layer. OXMIQ claims t…

Hot Chips 2026: Arm details AGI server CPU with two 70-core N3P chiplets — touts 2 TB/s UCIe fabric link and 12-channel memory controller

The important point is that CMN-S3 is not just an internal CPU mesh, as Arm designed the coherent system to extend outside of the die to extend coherency beyond the die and the socket. The approach is conceptually closer…

Hot Chips 2026: Intel dives deep on Crescent Island AI accelerator — larger caches and deeper XMX engines target maximum AI FLOPS per watt

As for the specific applications that Crescent Island will target, Intel highlights the rise of mixture-of-experts models paired with speculative decoding as a new class of workload that Crescent Island can serve well.

Hot Chips 2026: Micron warns HBM wafer penalty is widening with every generation — AI memory uses 3x more silicon than DDR5, company says memory wall is ‘gettin

Micron’s presentation put compute performance scaling at roughly three times every two years and HBM bandwidth at under two times, a divergence Sreeramaneni summarized by saying “the memory wall is still present, and, in…

Hot Chips 2026: Micron warns HBM wafer penalty is widening with every generation — AI memory uses 3x more silicon than DDR5, company says memory wall is ‘gettin

Micron’s presentation put compute performance scaling at roughly three times every two years and HBM bandwidth at under two times, a divergence Sreeramaneni summarized by saying “the memory wall is still present, and, in…

Hot Chips 2026: High Bandwidth Flash promises massive bandwidth and capacity, but its usability is extremely limited — new memory format strikes a balance betwe

Additionally, more local capacity could also reduce communication between accelerators. Conventional expert parallelism distributes experts across GPUs and requires all-to-all communication at every layer. OXMIQ claims t…

Hot Chips 2026: Nvidia presents Groq 3 LPX architecture and unveils its first third-party inference benchmark — LP30-based rack already in production, company s

An FPGA bridges the synchronous LPU domain and the asynchronous world of host I/O and GPU hand-offs, and Nvidia’s Dynamo runtime, together with an LPU extension to CUDA, orchestrates the split. The company put the gains …