Moving from 6×6-inch to 6×12-inch photomasks would require substantial changes across the existing mask ecosystem, including mask blanks and deposition, etching, inspection and metrology, cleaning, pellicles, mask writers, and mask handling systems. Crucially, High-NA EUV scanners would also have to be modified or redesigned to accommodate the larger masks, which will make the transition a major retooling effort across the semiconductor supply chain. While neither ASML nor Intel confirmed that existing or planned High-NA EUV scanners can be modified to handle larger masks, all of the future High-NA EUV scanners to be launched before and after 2033 are designed around 6×6-inch reticles and stitching, according to ASML's roadmap.
It remains to be seen whether the industry moves on to larger 6×12-inch photomasks, but Intel appears to be the main evangelist for changing the mask standard that has defined projection lithography infrastructure for decades. If the effort comes to fruition, then Intel will likely have a considerable first-mover advantage over its industry peers because it will define and set the standard for the projection lithography industry for decades to come, an advantage that is hard to overestimate.
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Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
mac2213 The reporting on the technical details in this article is outstanding, but it fails to recognize the confusing information that both Intel and ASML had pushed on the market regarding HNA tool deliveries starting in the spring of 2024. Even the recent comments by ASML at Semicon Taiwan 26 were intentionally misleading, but a bit closer to the truth where they talked about 4 HNA customers and 13 total HNA tools delivered, but failed to include IMEC and NY Crest Dev efforts in either count. It would be nice if Tom's could lead the reporting on the tool count and timing on delivery in their reporting. Restating the belief that Intel only has 3 or 4 tools out of 13 total (or 16 including IMEC/NYDEV) doing this kind of volume is confusing everyone further. Reply
moreslawplease mac2213 said: The reporting on the technical details in this article is outstanding, but it fails to recognize the confusing information that both Intel and ASML had pushed on the market regarding HNA tool deliveries starting in the spring of 2024. Even the recent comments by ASML at Semicon Taiwan 26 were intentionally misleading, but a bit closer to the truth where they talked about 4 HNA customers and 13 total HNA tools delivered, but failed to include IMEC and NY Crest Dev efforts in either count. It would be nice if Tom's could lead the reporting on the tool count and timing on delivery in their reporting. Restating the belief that Intel only has 3 or 4 tools out of 13 total (or 16 including IMEC/NYDEV) doing this kind of volume is confusing everyone further. Intel could have easily made a million wafers in this time with just one machine. Check ASML page for the 5000. Output is still 100+ per hour. It's not like they are claiming 1M fully finished wafers using every feature of high na… I'm not saying it's one but the million doesn't mean it needs to be more than one either. Reply
Stomx 1 Million, 1 Billion…Where is something I'd like to buy ? Reply
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Reference reading
- https://www.tomshardware.com/tech-industry/semiconductors/SPONSORED_LINK_URL
- https://www.tomshardware.com/tech-industry/semiconductors/intel-surpasses-one-million-high-na-euv-wafers-processed-outpaces-the-rest-of-the-industry-combined-company-also-trailblazing-giant-6-12-photomasks-to-speed-production-and-lower-costs1#main
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