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The bottom-gate layout puts the gate electrode beneath the channel, which captures the dopants that scatter deeper than intended during implantation, a channeling effect that had thrown conventional top-gate JFET thresholds off by more than 2V. With the channeling tail compensated, the design-to-measured threshold voltage gap dropped to under 0.1V at 400°C.
The double-well structure isolates each device inside a pn junction instead of leaning on the semi-insulating SiC substrate underneath, which loses its insulating behavior as it heats and bleeds leakage current through the wafer. Kaneko's group reported the remaining leakage sits close to the theoretical floor set by SiC's own material properties, so there's little room left to improve it at the device level.
In contrast, NASA Glenn Research Center has run SiC JFET integrated circuits carrying more than 175 transistors for over a year at 500°C in air, and 60 days on a simulated Venus surface at 460°C and 9.3 MPa with no shielding, per the agency's published testing. Those chips are built from epitaxial JFET-resistor devices on a bespoke process. The Kyoto researchers reached a higher device temperature through ion implantation, a method already standard across mainstream fabs, which fits existing mass production.
SiC is already scaling as a power-device wafer material , but high-temperature logic is a separate and far smaller niche. It isn't the only wide-bandgap material chased for these conditions either, with researchers recently showing devices that hold up from 500°C down toward absolute zero in other compounds.
Post-silicon era gets closer as industry giants crack the 2D transistor scaling bottleneck with breakthrough tech
Imec's 2026 roadmap details 0.3nm nodes by 2038, CFET transistors become viable at 0.7nm
Researchers create programmable material that can steer heat and remember its state without power
The transistor is normally-on, so it conducts with no gate voltage applied and draws standby power. Efficient logic needs complementary pairs built from normally-off devices, which this isn't. Kimoto's group has already demonstrated complementary SiC JFET logic gates at 350°C, and its next step is to design normally-off devices in the new structure to build low-power complementary circuits. Long-duration reliability at temperature and heat-tolerant packaging are just two challenges the researchers will need to overcome before any of it reaches a gas turbine, or Venus.
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