CXL is a protocol that sits on top of the PCIe physical interface. As a result of this, many early CXL implementations were built by modifying existing PCIe IP, which is why such implementations inherited architectural characteristics optimized for PCIe rather than for memory-semantic communications, which added substantial latency, according to Panmnesia. By contrast, its new CXL controller IP features a redesigned data path that replaces separate per-layer buffers with shared buffers to eliminate much of the synchronization overhead. In addition, it features additional latency optimizations throughout the protocol stack that offset the additional hop introduced by the switch.
The accompanying CXL fabric switch introduces Port-Based Routing (PBR), which removes the tree-topology limitations of conventional Hierarchy-Based Routing (HBR) used by PCIe and early CXL implementations. The fabric switch still supports both PBR and HBR to enable flexible system topologies, optimized traffic routing, and stable performance. In practice, it enables companies like Meta to install more DDR4 memory into their modern servers without major performance degradation because of high latency.
Panmnesia claims that while early CXL deployments could connect only a handful of compute nodes to shared memory pools, its fabric scales to up to 64 nodes, which means greater flexibility for hyperscalers that tend to run thousands of servers, but which now have to rationalize usage of expensive DRAM.
Panmnesia says its next-generation CXL technologies are progressing toward commercialization. The company has pre-release silicon for its PCIe 6.4/CXL 3.2 Fusion Switch and has completed development of its PCIe 7.0/CXL 4.0 Combo IP, which supports the latest features introduced by the CXL 4.0 specification.
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Anton Shilov is a contributing writer at Tom\u2019s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends. ","collapsible":{"enabled":true,"maxHeight":250,"readMoreText":"Read more","readLessText":"Read less"}}), "https://slice.vanilla.futurecdn.net/13-4-24/js/authorBio.js"); } else { console.error('%c FTE ','background: #9306F9; color: #ffffff','no lazy slice hydration function available'); } Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
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Key considerations
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Reference reading
- https://www.tomshardware.com/pc-components/dram/SPONSORED_LINK_URL
- https://www.tomshardware.com/pc-components/dram/meta-fights-soaring-hardware-costs-by-reusing-old-ddr4-server-memory-in-new-ddr5-only-servers-custom-cxl-2-0-chip-marries-legacy-ddr4-2400-with-cutting-edge-ddr5-6400#main
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